volume 24 issue 1 publication number 19

Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment

Ibrahim Rahmani 1, 2
ZOHIR DIBI 1, 3
Hichem Farhati 1, 3
Faycal Djeffal 1
Publication typeJournal Article
Publication date2024-12-09
scimago Q3
wos Q2
SJR0.333
CiteScore5.3
Impact factor2.5
ISSN15698025, 15728137
Abstract
We present a new subthreshold analytical model for dual-material junctionless gate-all-around negative capacitance field-effect transistors (DM JL GAA NCFETs). The model accurately reproduces the electrostatic potential distribution, subthreshold current characteristics of the device, threshold voltage, and subthreshold slope. By solving the Landau–Khalatnikov (L–K) equation with Poisson’s equation, the model provides a precise analytical solution that aligns closely with numerical results. The impact of various parameters such as channel length, DM gate ratio, and ferroelectric layer thickness on the device subthreshold behavior is systematically analyzed. It is found that the strategic combination between the JL structure and NC effect can allow achieving enhanced device performance at the nanoscale level. The results demonstrate that the optimized DM JL GAA NCFET exhibits enhanced short-channel performance at nanoscale level, reduced subthreshold swing of 49 mV/dec, lower threshold voltage of 0.20 V, and reduced OFF-current of 1.5 × 10–5 nA. Therefore, the proposed design framework strategy paves the way for designers not only to identify the appropriate DM gate configuration and the suitable ferroelectric material for the development of ultralow-power and high-performance nanoelectronic circuits.
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Rahmani I. et al. Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment // Journal of Computational Electronics. 2024. Vol. 24. No. 1. 19
GOST all authors (up to 50) Copy
Rahmani I., DIBI Z., Farhati H., Djeffal F. Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment // Journal of Computational Electronics. 2024. Vol. 24. No. 1. 19
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RIS Copy
TY - JOUR
DO - 10.1007/s10825-024-02241-x
UR - https://link.springer.com/10.1007/s10825-024-02241-x
TI - Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment
T2 - Journal of Computational Electronics
AU - Rahmani, Ibrahim
AU - DIBI, ZOHIR
AU - Farhati, Hichem
AU - Djeffal, Faycal
PY - 2024
DA - 2024/12/09
PB - Springer Nature
IS - 1
VL - 24
SN - 1569-8025
SN - 1572-8137
ER -
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@article{2024_Rahmani,
author = {Ibrahim Rahmani and ZOHIR DIBI and Hichem Farhati and Faycal Djeffal},
title = {Novel junctionless GAA negative capacitance FET based on gate engineering aspects: analytical modeling and performance assessment},
journal = {Journal of Computational Electronics},
year = {2024},
volume = {24},
publisher = {Springer Nature},
month = {dec},
url = {https://link.springer.com/10.1007/s10825-024-02241-x},
number = {1},
pages = {19},
doi = {10.1007/s10825-024-02241-x}
}