Thermal management of through-silicon vias and back-end-of-line layers in 3D ICs: A comprehensive review

Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.