volume 159 pages 106656

Negative capacitance double-gate MOSFET for advanced low-power electronic applications

Amit Kumar 1, 2
Saurabh Chaturvedi 1
Satyendra Kumar 1
2
 
Department of Electronics and Communication Engineering, Lloyd Institute of Engineering and Technology, Greater Noida, India
Publication typeJournal Article
Publication date2025-05-01
scimago Q3
wos Q3
SJR0.392
CiteScore4.3
Impact factor2.3
ISSN09598324, 00262692, 18792391
Abstract
The negative capacitance metal–oxide–semiconductor field-effect transistor (NC-MOSFET) has gained significant attention for its potential in low-power applications. This paper introduces a novel triple-material double-gate negative capacitance MOSFET (TM-DG-NC-MOSFET) architecture, analyzed through technology computer-aided design (TCAD) simulations to assess its DC, analog, linearity, and distortion performance characteristics. For comparison, a triple-material double-gate MOSFET (TM-DG-MOSFET) without the negative capacitance effect is also designed and simulated. Key device parameters are optimized for both architectures. TCAD simulation results at VDS = 0.1 V reveal that the TM-DG-NC-MOSFET achieves a subthreshold swing of 25 mV/decade, an on-state current of 3.19×10−3 A/μm, and a switching ratio of 5.13×107, outperforming the baseline TM-DG-MOSFET, which exhibits a subthreshold swing of 77 mV/decade, an on-state current of 0.83×10−3 A/μm, and a switching ratio of 1.34×107. Comparative analysis shows that the TM-DG-NC-MOSFET offers enhanced DC, analog, and linearity performance with reduced distortion, indicating its suitability as a promising candidate for low-power circuit applications.
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Kumar A. et al. Negative capacitance double-gate MOSFET for advanced low-power electronic applications // Microelectronics Journal. 2025. Vol. 159. p. 106656.
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Kumar A., Chaturvedi S., Kumar S. Negative capacitance double-gate MOSFET for advanced low-power electronic applications // Microelectronics Journal. 2025. Vol. 159. p. 106656.
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TY - JOUR
DO - 10.1016/j.mejo.2025.106656
UR - https://linkinghub.elsevier.com/retrieve/pii/S1879239125001055
TI - Negative capacitance double-gate MOSFET for advanced low-power electronic applications
T2 - Microelectronics Journal
AU - Kumar, Amit
AU - Chaturvedi, Saurabh
AU - Kumar, Satyendra
PY - 2025
DA - 2025/05/01
PB - Elsevier
SP - 106656
VL - 159
SN - 0959-8324
SN - 0026-2692
SN - 1879-2391
ER -
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@article{2025_Kumar,
author = {Amit Kumar and Saurabh Chaturvedi and Satyendra Kumar},
title = {Negative capacitance double-gate MOSFET for advanced low-power electronic applications},
journal = {Microelectronics Journal},
year = {2025},
volume = {159},
publisher = {Elsevier},
month = {may},
url = {https://linkinghub.elsevier.com/retrieve/pii/S1879239125001055},
pages = {106656},
doi = {10.1016/j.mejo.2025.106656}
}