volume 25 issue 15 pages 6125-6133

CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation

Yujia Yan 1, 2, 3, 4, 5, 6, 7, 8
Tao Yan 9, 10
Feng Wang 7, 8, 11, 12
Yuhan Zhu 7, 8, 11, 12
Shuhui Li 3, 4, 7, 8
Shu Hui Li 7, 8
Yuchen Cai 3, 4, 7, 8, 11, 12, 13, 14
Fuyuan Zhang 7, 8, 11, 12, 15
Yanrong Wang 16, 17, 18, 19
Xiaolin Liu 1, 2, 5, 6
Kai Xu 20, 21
Jun He 22, 23, 24, 25
Xueying Zhan 3, 4, 7, 8
Jia Lin 1, 2, 5, 6
Zhenxing Wang 3, 4, 7, 8, 11, 12, 13, 14
1
 
Department of Physics, Shanghai Key Laboratory of Materials Protection and Advanced Materials in Electric Power
3
 
CAS Key Laboratory of Nanosystem and Hierarchical Fabrication
5
 
Department of Physics, Shanghai Key Laboratory of Materials Protection and Advanced Materials in Electric Power, Shanghai, P. R. China
7
 
CAS Key Laboratory of Nanosystem and Hierarchical Fabrication, Beijing, P. R. China
9
 
Beijing National Laboratory for Condensed Matter Physics, Beijing, China
11
 
Center of Materials Science and Optoelectronics Engineering, Beijing, P. R. China
13
 
Center of Materials Science and Optoelectronics Engineering
15
 
School of Advanced Interdisciplinary Sciences, Beijing, P. R. China
16
 
Institute of Semiconductors
17
 
Henan Academy Of Sciences
18
 
Institute of Semiconductors, Zhengzhou, P. R. China
19
 
Henan Academy of Sciences, Zhengzhou, P. R. China
20
 
Hangzhou Global Scientific and Technological Innovation Center, School of Micro-Nano Electronics, Hangzhou, China
22
 
Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, School of Physics and Technology
24
 
Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education, School of Physics and Technology, Wuhan, P. R. China
Publication typeJournal Article
Publication date2025-04-03
scimago Q1
wos Q1
SJR2.967
CiteScore14.9
Impact factor9.1
ISSN15306984, 15306992
Abstract
Two-dimensional (2D) semiconductors are potential candidates for advanced technology nodes, but their integration with silicon lines remains a significant challenge. Here, we present a high-k dielectric van der Waals encapsulation strategy for the fabrication of 2D semiconductor-based complementary field-effect transistors (CFETs) compatible with established processes. This technique, involving the transfer of a high-k dielectric onto 2D semiconductors, protects channels from polymer contamination, enables O2 plasma surface cleaning, and facilitates the following dielectric depositions without doping or damage. The strategy results in heterostructures and devices with reduced surface roughness and is applicable to both p- and n-type semiconductors, including MoS2, WS2, MoTe2, and black phosphorus. Utilizing this method, we have successfully fabricated 2D CFET inverters with a gain of up to 19.54 and power consumption as low as 2.63 nW. Our work paves the way for the integration of 2D semiconductors with silicon technology, therefore accelerating the lab-to-fab transition progress.
Found 
Found 

Are you a researcher?

Create a profile to get free access to personal recommendations for colleagues and new articles.
Metrics
4
Share
Cite this
GOST |
Cite this
GOST Copy
Yan Y. et al. CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation // Nano Letters. 2025. Vol. 25. No. 15. pp. 6125-6133.
GOST all authors (up to 50) Copy
Yan Y. et al. CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation // Nano Letters. 2025. Vol. 25. No. 15. pp. 6125-6133.
RIS |
Cite this
RIS Copy
TY - JOUR
DO - 10.1021/acs.nanolett.5c00220
UR - https://pubs.acs.org/doi/10.1021/acs.nanolett.5c00220
TI - CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation
T2 - Nano Letters
AU - Yan, Yujia
AU - Yan, Tao
AU - Wang, Feng
AU - Zhu, Yuhan
AU - Li, Shuhui
AU - Li, Shu Hui
AU - Cai, Yuchen
AU - Zhang, Fuyuan
AU - Wang, Yanrong
AU - Liu, Xiaolin
AU - Xu, Kai
AU - He, Jun
AU - Zhan, Xueying
AU - Lin, Jia
AU - Wang, Zhenxing
PY - 2025
DA - 2025/04/03
PB - American Chemical Society (ACS)
SP - 6125-6133
IS - 15
VL - 25
SN - 1530-6984
SN - 1530-6992
ER -
BibTex |
Cite this
BibTex (up to 50 authors) Copy
@article{2025_Yan,
author = {Yujia Yan and Tao Yan and Feng Wang and Yuhan Zhu and Shuhui Li and Shu Hui Li and Yuchen Cai and Fuyuan Zhang and Yanrong Wang and Xiaolin Liu and Kai Xu and Jun He and Xueying Zhan and Jia Lin and Zhenxing Wang and others},
title = {CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation},
journal = {Nano Letters},
year = {2025},
volume = {25},
publisher = {American Chemical Society (ACS)},
month = {apr},
url = {https://pubs.acs.org/doi/10.1021/acs.nanolett.5c00220},
number = {15},
pages = {6125--6133},
doi = {10.1021/acs.nanolett.5c00220}
}
MLA
Cite this
MLA Copy
Yan, Yujia, et al. “CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation.” Nano Letters, vol. 25, no. 15, Apr. 2025, pp. 6125-6133. https://pubs.acs.org/doi/10.1021/acs.nanolett.5c00220.