Inductance of superconductor integrated circuit features with sizes down to 120 nm

Jackman K., Fourie C.J.

Tolpygo S.K., Semenov V.K.

Abstract We review the existing fabrication processes for superconductor digital electronics and describe approaches to increasing the scale of integration of superconducting digital circuits from the current level of about one million Josephson junctions (JJs) on a 1-cm2 chip toward ten million JJs per chip. We present designs of ac-clocked Single Flux Quantum (SFQ) shift registers, convenient benchmarking circuits, in a 250-nm-linewidth superconductor electronics fabrication process developed recently at MIT Lincoln Laboratory (MIT LL). For shift registers using resistively shunted JJs with Josephson critical current density, J c of 100 μA/μm2, we achieved a record-high circuit density of 4.2·106 JJs per cm2, a factor of three higher than the previous record obtained in the MIT LL 350-nm-linewidth SFQ5ee process. Using self-shunted JJs with J c of 600 μA/μm2, we increased this record circuit density to 7.4·106 JJs per cm2.

Semenov V.K., Polyakov Y.A., Tolpygo S.K.

Arrays of vortex transitional (VT) memory cells with functional density up to 1 Mbit/cm 2 have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-μA/μm 2 MIT LL fabrication process SFQ5ee with eight niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied 168 μm 2 , resulting in an over 0.5 Mbit/cm 2 functional density. Then, we reduced the cell area down to 99 μm 2 (corresponding to over 0.9 Mbit/cm 2 functional density) by utilizing self-shunted Josephson junctions (JJs) with critical current density JC of 600 μA/μm 2 and eliminating shunt resistors. The fabricated high-JC memory cells were fully operational and possessed wide read/write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: 1) miniaturization of superconducting transformers by using soft magnetic materials; and 2) reduction of JJ area by using planar high-JC junctions similar to variable thickness bridges.

Tolpygo S.K., Bolkhovsky V., Rastogi R., Zarr S., Day A.L., Golden E., Weir T.J., Wynn A., Johnson L.M.

In superconductor electronics fabrication processes developed at MIT Lincoln Laboratory, Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten superconducting layers. We discuss the effects of this placement and other processing factors on uniformity of JJ critical current across 200-mm wafers; specifically, nonuniformity of residual stress in Nb films, wafer bow and warpage caused by accumulated stress in the underlying dielectric and superconducting layers, and effects of accumulated topography caused by patterning and planarization of wiring layers. We describe the typical fabrication defects, focusing primarily on the peculiar defects caused by electrochemical corrosion of dissimilar metals. To increase the integration scale and enhance fabrication capabilities, we are developing a new process, titled SC1, in which Nb/Al/AlO x /Nb JJs are placed near the bottom of the layer stack, preceded only by two planarized layers: resistor layer and superconducting ground plane. Six planarized Nb wiring layers are placed above the JJs. This layer stack should simplify routing of data and clock in integrated circuits, and allow for improvements in uniformity of small JJs. The SC1 process has a 250-nm minimum feature size for inductors, three sheet resistance options for resistors, and two options for JJ critical current density: 100 and 200 μA/μm 2 . We present fabrication details and process optimization aimed at improving JJ uniformity, increasing circuit yield, and reducing occurrence of corrosion defects to below the 1 ppm level.

Tolpygo S.K., Bolkhovsky V., Oates D.E., Rastogi R., Zarr S., Day A.L., Weir T.J., Wynn A., Johnson L.M.

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on ${\text{1}}\hbox{-}{\text{cm}}^{2}$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlOx–Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high- $J_{{\rm{c}}}$ JJs and compact thin-film MoNx kinetic inductors instead of geometrical inductors. We present fabrication details and properties of ${\text{MoN}}_{x}$ films with a wide range of $T_{{\rm{c}}}$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth $\lambda _{0}$. As kinetic inductors, we implemented Mo2 N films with $T_{{\rm{c}}}$ about 8 K, $\lambda _{0}$ about 0.51 μm, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlOx tunnel barriers and $J_{{\rm{c}}}= {\text{0.6}}\,{\text{mA}}{/}\mu{\text{m}}^{2}$ , and with 10-nm thick Si1−xNbx barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si1−xNb x barriers at $x< {{0.08}}$ is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlOx tunnel barriers.

Tolpygo S.K., Bolkhovsky V., Rastogi R., Zarr S., Day A.L., Weir T.J., Wynn A., Johnson L.M.

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

Oates D.E., Tolpygo S.K., Bolkhovsky V.

We report results of measurements of Nb stripline resonators with linewidths ranging from 1.0 to 0.25 μ m, fabricated using an 8-Nb-layer process with planarized SiO2 dielectric developed at MIT Lincoln Laboratory for superconductor single-flux-quantum circuits. The fundamental resonant frequency f 0 was varied from 2.3 to 4.5 GHz. The results show that, at 4 K, the losses for the narrowest lines are dominated by losses in the dielectric. At high power, the nonlinear niobium losses dominate. Spiral inductors have also been used to design and fabricate multipole low-pass filters with three and five poles with cutoff at 1 GHz. The measured and simulated results for the filters agree very well and show almost ideal properties. The precision and high reproducibility of this fabrication process hold the promise of fabricating multipole filters without the need for tuning the individual poles.

Semenov V.K., Polyakov Y.A., Tolpygo S.K.

We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106 cm−2 junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.

Tolpygo S.K., Bolkhovsky V., Zarr S., Weir T.J., Wynn A., Day A.L., Johnson L.M., Gouker M.A.

We investigated current–voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities Jc in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits as well as to assess their potential for future technology nodes. Nb/AlOx-Al/Nb junctions with diameters from 0.5 to 6 μm were fabricated using a fully planarized process with Mo or MoNx thin-film shunt resistors with sheet resistance Rsq = 2 Ω/sq and Rsq = 6 Ω/sq, respectively. We used our current standard MIT Lincoln Laboratory process node SFQ5ee to fabricate JJs with Jc = 0.1 mA/μm2 and our new process node SFQ5hs (where “hs” stands for high speed) to make JJs with Jc = 0.2 mA/μm 2 and higher current densities up to about 1 mA/μm2. Using LRC resonance features on the I–V characteristics of shunted JJs, we extract the inductance associated with Mo shunt resistors of 1.4 pH/sq. The main part of this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to “kinetic” inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency $\boldsymbol{\omega },$ ${{\mathbf \sigma }}(\boldsymbol{\omega }) = {\boldsymbol{\sigma }_0}/({1 + \boldsymbol{i\omega \tau }})$, where ${{{\mathbf \sigma }}_0}$ is the static conductivity and $\boldsymbol{\tau }$ the electron scattering time. Using a resonance in a large-area unshunted high-Jc junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high-J c junctions in 0.1–1 mA/μm2 Jc range. We also present data on Jc targeting and JJ critical current spreads. We discuss the potential of using 0.2-mA/μm2 JJs in very large scale integration single flux quantum circuits and 0.5-mA/μm2 JJs in high-density integrated circuits without shunt resistors.

Fourie C.J., Shawawreh C., Vernik I.V., Filippov T.V.

The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.

Shukrinov Y.M., Rahmonov I.R., Kulikov K.V., Botha A.E., Plecenik A., Seidel P., Nawrocki W.

Resonance phenomena in a model of intrinsic Josephson junctions shunted by LC-elements (L-inductance, C-capacitance) are studied. The phase dynamics and IV-characteristics are investigated in detail when the Josephson frequency approaches the frequency of the resonance circuit. A realization of parametric resonance through the excitation of a longitudinal plasma wave, within the bias current interval corresponding to the resonance circuit branch, is demonstrated. It is found that the temporal dependence of the total voltage of the stack, and the voltage measured across the shunt capacitor, reflect the charging of superconducting layers, a phenomenon which might be useful as a means of detecting such charging experimentally. Thus, based on the voltage dynamics, a novel method for the determination of charging in the superconducting layers of coupled Josephson junctions is proposed. A demonstration and discussion of the influence of external electromagnetic radiation on the IV-characteristics and charge-time dependence is given. Over certain parameter ranges the radiation causes an interesting new type of temporal splitting in the charge-time oscillations within the superconducting layers.

Tolpygo S.K.

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 107 Josephson junctions per cm2 is described.

Semenov V.K., Khapaev M.M.

Trapping of residual magnetic field degrades the performance and, in extreme cases, destroys operability of superconductor digital circuits. It is known that moats or narrow cuts made in superconductor thin films are able to “immunize” them from flux trapping. So far, an intuition rather than science has played a more significant role in the selection of geometry and density of these moats. We formalized an estimation of the moat efficiency. This procedure involves the calculation of Gibbs potentials of arbitrary shaped films in a magnetic field and comparison of the potentials with and without vortices in the film and magnetic flux frozen in the moats. We numerically simulate evolutions of the Gibbs potentials of films slowly cooled in a constant residual magnetic field. The simulations allow forecasting equilibrium distributions of vortices and fluxes trapped in the moats corresponding to the lowest potentials. The superconductor film becomes immune to the trapping Pearl vortices if the lowest Gibbs potential can be achieved without such Pearl vortices.

Jackman K., Fourie C.

We have developed a new 3-D numerical engine that we call TetraHenry and that uses tetrahedral volume elements to discretize complex geometries. Volume loop basis functions are used to discretize the volume integral equation to obtain the method-of-moments matrix equation. The fast multipole method used in FastHenry has been modified to support the conventional Schaubert-Wilton-Glisson basis functions. We demonstrate the validity and capabilities of this method by extracting the inductance from several superconducting structures and comparing the results to those obtained with FastHenry.

Tolpygo S., Bolkhovsky V., Weir T., Wynn A., Oates D., Johnson L., Gouker M.

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc

Meninger S.E., Tolpygo S.K.

Chen M., Ying L., Li L., Zhang X., Wu Y., Shi W., Xie H., Ma L., Ren J.

Gretsch R., Sherwood T.

Schegolev Andrey E., Bastrakova Marina V., Sergeev Michael A., Maksimovskaya Anastasia A., Klenov Nikolay V., Soloviev Igor

The extensive development of the field of spiking neural networks has led to many areas of research that have a direct impact on people’s lives. As the most bio-similar of all neural networks, spiking neural networks not only allow for the solution of recognition and clustering problems (including dynamics), but they also contribute to the growing understanding of the human nervous system. Our analysis has shown that hardware implementation is of great importance, since the specifics of the physical processes in the network cells affect their ability to simulate the neural activity of living neural tissue, the efficiency of certain stages of information processing, storage and transmission. This survey reviews existing hardware neuromorphic implementations of bio-inspired spiking networks in the ”semiconductor”, ”superconductor”, and ”optical” domains. Special attention is given to the potentials for effective ”hybrids” of different approaches.

Zhong Y., Zhang L., Xie J., Zheng Z., Lu M., Jin H., Wu L., Shi W., Wang H., Peng W., Chen L., Wang Z.

Abstract In this paper, we report on a systematic study of the inductance and magnetic field penetration depth (λ) of polycrystalline NbN superconducting thin films. By employing a four-metal-layer fabrication process specifically designed for all-NbN single-flux-quantum circuits, we constructed a superconducting quantum interference device loop composed of two parallel NbN SNS junctions, NbN microstrips, and NbN ground planes for precise inductance measurement. At 4.2 K, as the linewidth increases from 1 μm to 30 μm, the inductance per unit length (L u) of NbN microstrips significantly decreases, for example, the L u of 250 nm thick NbN microstrips drops from 0.907 pH/μm to 0.047 pH/μm. Compared to Nb, the L u of polycrystalline NbN microstrips is approximately two to three times that of Nb, offering an advantage for manufacturing smaller superconducting inductors. Furthermore, we conducted simulation analysis using InductEx software to extract the λ of NbN films of varying thicknesses. The results indicate that as the film thickness increased from 45 nm to 600 nm, λ initially decreased sharply and then stabilized, with values ranging from 430 nm to 323 nm. Notably, once the film thickness exceeded 200 nm, λ remained essentially constant, even at a temperature of 10 K, where it showed good stability, albeit with a slight increase (about 50 nm) compared to 4.2 K. This dependence of λ on thickness is reasonably explained by considering the effects of NbN film thickness on the superconducting critical temperature and residual resistivity. These research findings not only deepen our understanding of the characteristics of superconducting films but also lay a solid foundation for the future design and manufacture of more compact superconducting circuits at the higher temperature of 10 K.

Zhong Y., Zhang L., Xie J., Zheng Z., Lu M., Jin H., Wu L., Shi W., Wang H., Peng W., Chen L., Wang Z.

Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density (J c) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm−2 for a 15 nm barrier to 12.8 ± 1.9 kA cm−2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm−2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage (I–V) characteristics. Especially for junctions with diameter (φ) ranging from 0.8 to 1.6 μm, their critical current (I c) falls within the range of 110–450 μA, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I–V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.

Bairamkulov R., De Micheli G.

Tolpygo S.K., Rastogi R., Weir T., Golden E.B., Bolkhovsky V.

Mitrovic A., Friedman E.G.

Garcia C.A., Bailey N., Kirby C., Strong J.A., Talanov V.V., Herr A.Y., Anlage S.M.

An understanding of the origins of power loss in superconducting interconnects is essential for the energy efficiency and scalability of superconducting digital logic. At microwave frequencies, power dissipates in both the superconducting wires and the dielectric and these losses can be of comparable magnitude. We describe an approach to accurately disentangle such losses by exploiting their frequency dependence in a multimode transmission-line resonator. This is supported by the concept of a resonator geometric factor extracted from the Ansys High Frequency Structure Simulator (hfss), a commercial three-dimensional finite-element method (FEM) that we adopt for solving a superconductor interior. Using the technique, we have optimized a planarized fabrication process of reciprocal quantum logic (RQL) for the minimum interconnect loss at 4.2 K and gigahertz frequencies. The microstrip interconnects are composed of niobium ($\mathrm{Nb}$) insulated by silicon dioxide ($\mathrm{Si}\mathrm{O}$${}_{2}$) made from a tetraethoxysilane (TEOS) precursor. Two process generations use damascene fabrication and the third one uses Cloisonn\'e fabrication. For all three, $\mathrm{Si}\mathrm{O}$${}_{2}$ exhibits a dielectric loss tangent $\mathrm{tan}\phantom{\rule{0.1em}{0ex}}\ensuremath{\delta}=0.0012\ifmmode\pm\else\textpm\fi{}0.0001$, independent of the $\mathrm{Nb}$ wire width over 0.25--4 $\text{\ensuremath{\mu}}\mathrm{m}$. The intrinsic microwave resistance ${R}_{s}$ of $\mathrm{Nb}$ varies with both the process and the wire width. For damascene fabrication, scanning transmission electron microscopy (STEM) and energy-dispersive x-ray spectroscopy (EDS) reveal that plasma oxidation and grain-growth orientation increase ${R}_{s}$ above the Bardeen-Cooper-Schrieffer (BCS) resistance ${R}_{\mathrm{BCS}}\ensuremath{\approx}17\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}\mathrm{\ensuremath{\Omega}}$ at 10 GHz. For Cloisonn\'e fabrication, we demonstrate ${R}_{s}=13\ifmmode\pm\else\textpm\fi{}1.4\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}\mathrm{\ensuremath{\Omega}}$ down to $0.25\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}\mathrm{m}$ wire width, which is below ${R}_{\mathrm{BCS}}$ and arguably the lowest microwave resistance reported for $\mathrm{Nb}$ at 4.2 K.

Jabbari T., Friedman E.G.

Krylov G., Jabbari T., Friedman E.G.

Superconductive single flux quantum (SFQ) technology is one of the most promising beyond CMOS technologies for large-scale, high-performance computing systems. The operating frequency of SFQ circuits may exceed hundreds of gigahertz while dissipating several orders of magnitude lower power, including the refrigeration. Recent advances in SFQ manufacturing technology have enabled significantly higher levels of integration and system complexity. Further advancements in SFQ systems integration require improved design methodologies and flows. The lack of SFQ specific benchmark systems complicates the development and evaluation of these SFQ design flows. This limitation is particularly relevant to the development of physical design tools since existing CMOS benchmark systems are not easily adapted to support SFQ technology. In this chapter, a suite of SFQ specific interconnect routing benchmark systems is presented. The benchmark circuits support the evaluation of data signal, clock signal, and bias current routing algorithms. Due to the gate-level pipelining inherent to SFQ logic, path balancing using D flip flops is required to ensure consistent logic depth and correct operation. Popular CMOS benchmark circuits are converted into SFQ technology, producing SFQ circuits with over 100,000 logic gates. Based on Synopsys EDA tools, the layout of these systems is generated for the MIT LL SFQ5ee technology. Rows of logic cells and passive transmission lines are also included within the layout to manage the interconnect length and delay. The benchmark circuits are openly available to evaluate and enhance state-of-the-art and next-generation physical design of VLSI complexity SFQ systems.

Krylov G., Jabbari T., Friedman E.G.

The all-JJ logic family is a promising area and power-efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this chapter, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, not requiring large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS’85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve the parameter margins.

Krylov G., Jabbari T., Friedman E.G.

Superconductive electronics based on Josephson junctions (JJ) is a promising cryogenic alternative technology to complementary metal oxide semiconductor (CMOS) technology for ultralow energy, high-speed stationary applications. For complex superconductive systems, the automated routing process determines the topology and methodology to connect cells while satisfying design constraints. On-chip signal routing has become an issue of growing importance in modern superconductive technologies; particularly, single flux quantum (SFQ) systems. Specialized routing methods for these systems are required. These routing methods include passive transmission lines (PTLs) and Josephson transmission lines behaving as interconnects. A primary issue within a long SFQ interconnect is the effects of resonance due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology to reduce and manage these resonance effects is required for driving long and short interconnect in VLSI complexity SFQ systems. Permissible interconnect lengths are suggested to ensure that the reflections do not affect the returning signals. The microwave behavior of the interconnect striplines is also considered to accurately estimate the surface inductance of the lines. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is discussed. Another primary issue within SFQ circuits is coupling noise between transmission striplines, degrading performance, and decreasing margins. Inductive and capacitive coupling noise between the routing layers, for the MIT LL SFQ5ee process, is described. An analysis of inductive and capacitive coupling noise can determine the minimum physical spacing between lines to enhance the automated routing process in large-scale systems. The increasing complexity of modern SFQ circuits has also made the issue of flux trapping of growing importance. The use of wide striplines for signal routing has exacerbated this issue. Trapped residual magnetic fields within the striplines damage the operability of superconductive circuits. Area-efficient topologies for striplines are introduced to manage flux trapping in large-scale SFQ circuits. These topologies are composed of several narrow lines rather than a single wide stripline. The first approach is a narrow parallel line topology in series with small resistors where each narrow line is connected to a single small resistor and via. The resistors in the parallel line topology remove any trapped fluxons and break any loops while requiring additional vias. The second topology is a fingered narrow line topology. The fingered narrow line topology enhances the scalability of SFQ systems while not requiring additional area and vias. These topologies require significantly less area while preventing flux from being trapped within wide superconductive striplines and reducing coupling noise between striplines. These methodologies and techniques are intended as guidelines to enable robust routing with superconductive interconnects. With these and other advances in design methodologies for superconductive electronics, the complexity of SFQ circuits is expected to greatly increase.

Krylov G., Jabbari T., Friedman E.G.

The phenomenon of superconductivity produces ideal diamagnetism in low Tc superconductors, contradicting the ferromagnetism phenomena. Superconductivity prefers antiparallel spin orientation of the electrons in Cooper pairs, whereas ferromagnetism forces the spins to be aligned in a parallel orientation. The combination of superconductivity and ferromagnetism is attracting significant attention as a promising electronic device for large-scale integrated superconductive systems. These superconductive-ferromagnetic devices are typically composed of different number, type, and configuration of superconductive, normal metal, ferromagnetic, and insulating layers. The primary objective of these devices is to enable area and power-efficient superconductive logic. In this chapter, the physics of ferromagnetic Josephson junctions and other types of ferromagnetic JJs is reviewed.