IEEE Journal of Solid-State Circuits, volume 31, issue 4, pages 504-513
A 286 MHz 64-b floating point multiplier with enhanced CG operation
1
Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
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Publication type: Journal Article
Publication date: 1996-04-01
Journal:
IEEE Journal of Solid-State Circuits
Q1
Q1
SJR: 2.876
CiteScore: 11.0
Impact factor: 4.6
ISSN: 00189200, 1558173X
DOI:
10.1109/4.499726
Electrical and Electronic Engineering
Abstract
This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics (CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TGs). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of "CG multiplication" that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5-/spl mu/m CMOS technology with triple-level metal of interconnection. The active area size is 4.2/spl times/5.1 mm/sup 2/. The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz. Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path.
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MAKING H. et al. A 286 MHz 64-b floating point multiplier with enhanced CG operation // IEEE Journal of Solid-State Circuits. 1996. Vol. 31. No. 4. pp. 504-513.
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MAKING H., Suzuki H., Morinaka H., Nakase Y., Mashiko K., Sumi T. A 286 MHz 64-b floating point multiplier with enhanced CG operation // IEEE Journal of Solid-State Circuits. 1996. Vol. 31. No. 4. pp. 504-513.
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RIS
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TY - JOUR
DO - 10.1109/4.499726
UR - https://doi.org/10.1109/4.499726
TI - A 286 MHz 64-b floating point multiplier with enhanced CG operation
T2 - IEEE Journal of Solid-State Circuits
AU - MAKING, Hirofumi
AU - Suzuki, Hiroshi
AU - Morinaka, H
AU - Nakase, Y.
AU - Mashiko, K
AU - Sumi, Takahiro
PY - 1996
DA - 1996/04/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 504-513
IS - 4
VL - 31
SN - 0018-9200
SN - 1558-173X
ER -
Cite this
BibTex (up to 50 authors)
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@article{1996_MAKING,
author = {Hirofumi MAKING and Hiroshi Suzuki and H Morinaka and Y. Nakase and K Mashiko and Takahiro Sumi},
title = {A 286 MHz 64-b floating point multiplier with enhanced CG operation},
journal = {IEEE Journal of Solid-State Circuits},
year = {1996},
volume = {31},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {apr},
url = {https://doi.org/10.1109/4.499726},
number = {4},
pages = {504--513},
doi = {10.1109/4.499726}
}
Cite this
MLA
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MAKING, Hirofumi, et al. “A 286 MHz 64-b floating point multiplier with enhanced CG operation.” IEEE Journal of Solid-State Circuits, vol. 31, no. 4, Apr. 1996, pp. 504-513. https://doi.org/10.1109/4.499726.