IEEE Micro, volume 19, issue 3, pages 47-55
Verifying the FM9801 microarchitecture
1
Lab. of Res., IBM Corp., Austin, TX, USA
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Publication type: Journal Article
Publication date: 1999-01-01
Electrical and Electronic Engineering
Hardware and Architecture
Software
Abstract
Hardware verification accounts for a considerable portion of the costs in the microprocessor design process. Traditionally designers have verified microprocessor designs using simulation techniques that help find most design faults. However, simulation never guarantees the correct operation of the final product. Some design faults are very difficult to detect by simulation; they may slip through the verification process into manufactured chips, raising costs. We believe that verification costs can be reduced by the judicious application of formal methods, which should lower the overall costs of design.
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TY - JOUR
DO - 10.1109/40.768503
UR - https://doi.org/10.1109/40.768503
TI - Verifying the FM9801 microarchitecture
T2 - IEEE Micro
AU - HUNT, W. A.
AU - Sawada, Jun
PY - 1999
DA - 1999/01/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 47-55
IS - 3
VL - 19
SN - 0272-1732
SN - 1937-4143
ER -
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@article{1999_HUNT,
author = {W. A. HUNT and Jun Sawada},
title = {Verifying the FM9801 microarchitecture},
journal = {IEEE Micro},
year = {1999},
volume = {19},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {jan},
url = {https://doi.org/10.1109/40.768503},
number = {3},
pages = {47--55},
doi = {10.1109/40.768503}
}
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HUNT, W. A., and Jun Sawada. “Verifying the FM9801 microarchitecture.” IEEE Micro, vol. 19, no. 3, Jan. 1999, pp. 47-55. https://doi.org/10.1109/40.768503.