volume 4 issue 12 pages 438-440

Epitaxial layer enhancement of n-well guard rings for CMOS circuits

R R Troutman 1
1
 
IBM General Technology Division, Burlington, VT
Publication typeJournal Article
Publication date1983-12-01
scimago Q1
wos Q2
SJR1.150
CiteScore7.6
Impact factor4.5
ISSN07413106, 15580563
Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering
Abstract
n-well guard rings have long been used for isolating potential electron injectors to avoid latch-up of CMOS circuits. Such guard rings are shown to be orders of magnitude more efficient for CMOS fabricated in an epitaxial layer (epi-CMOS) than for bulk (non-epi) CMOS. The maximum escape probability in epi-CMOS measures 3.9E-06 while for bulk CMOS it is 1.8E-02.
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GOST |
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GOST Copy
Troutman R. R. Epitaxial layer enhancement of n-well guard rings for CMOS circuits // IEEE Electron Device Letters. 1983. Vol. 4. No. 12. pp. 438-440.
GOST all authors (up to 50) Copy
Troutman R. R. Epitaxial layer enhancement of n-well guard rings for CMOS circuits // IEEE Electron Device Letters. 1983. Vol. 4. No. 12. pp. 438-440.
RIS |
Cite this
RIS Copy
TY - JOUR
DO - 10.1109/EDL.1983.25794
UR - https://doi.org/10.1109/EDL.1983.25794
TI - Epitaxial layer enhancement of n-well guard rings for CMOS circuits
T2 - IEEE Electron Device Letters
AU - Troutman, R R
PY - 1983
DA - 1983/12/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 438-440
IS - 12
VL - 4
SN - 0741-3106
SN - 1558-0563
ER -
BibTex |
Cite this
BibTex (up to 50 authors) Copy
@article{1983_Troutman,
author = {R R Troutman},
title = {Epitaxial layer enhancement of n-well guard rings for CMOS circuits},
journal = {IEEE Electron Device Letters},
year = {1983},
volume = {4},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {dec},
url = {https://doi.org/10.1109/EDL.1983.25794},
number = {12},
pages = {438--440},
doi = {10.1109/EDL.1983.25794}
}
MLA
Cite this
MLA Copy
Troutman, R. R.. “Epitaxial layer enhancement of n-well guard rings for CMOS circuits.” IEEE Electron Device Letters, vol. 4, no. 12, Dec. 1983, pp. 438-440. https://doi.org/10.1109/EDL.1983.25794.