Impact of wafer thinning on front-end reliability for 3D integration

Adrian Chasin ^{1, 2}

Mirko Scholz ^{1, 2}

W.H. Guo ^{1, 2}

J.A. Franco ^{1, 2}

Goedele Potoms ^{1, 2}

A. Jourdain ^{1, 2}

Dimitri Linten ^{1, 2}

Geert Van der Plas ^{1, 2}

Philippe Absil ^{1, 2}

Eric Beyne ^{1, 2}

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Kapeldreef 75 Leuven Belgium |

Publication type: Proceedings Article

Publication date: 2016-04-01

Institute of Electrical and Electronics Engineers (IEEE)

DOI: 10.1109/IRPS.2016.7574562

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Abstract

The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.

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IEEE Transactions on Electron Devices	IEEE Transactions on Electron Devices, 1, 16.67% IEEE Transactions on Electron Devices 1 publication, 16.67%
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Institute of Electrical and Electronics Engineers (IEEE)	Institute of Electrical and Electronics Engineers (IEEE), 3, 50% Institute of Electrical and Electronics Engineers (IEEE) 3 publications, 50%
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Impact of wafer thinning on front-end reliability for 3D integration

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