Latchup in bulk FinFET technology

C.-T. Dai ^{1, 2, 3}

S. H. Chen ⁴

D. Linten ⁴

M. Scholz ⁴

Geert Hellings ⁴

R Boschke ^{1, 2}

J Karp ⁵

Michael J Hart ⁵

Guido Groeseneken ^{1, 2}

Ming-Dou Ker ⁶

A. Mocuta ⁴

Naoto Horiguchi ⁴

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Electrical Engineering Dept., Katholieke Universiteit Leuven, Leuven, Belgium |

IMEC, Leuven, Belgium |

Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan |

⁴

imec, Kapeldreef 75, B‐3001 Leuven, Belgium |

⁵

Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, USA |

⁶

Institute of Electronics, National Chiao-Tung University, 30010 Hsinchu, Taiwan |

Publication type: Proceedings Article

Publication date: 2017-04-01

Institute of Electrical and Electronics Engineers (IEEE)

DOI: 10.1109/IRPS.2017.7936368

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Abstract

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

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