An FPGA-Based Emulator and Test System for the 3D-SOI chip CPV-4

Combining 3-D vertical integration technology for the silicon-on-insulator (SOI) pixel process, the compact pixel for vertex-4 (CPV-4) 3-D chip integrates sensing diode and analog front-end functions into the lower chip, while hit information storage and readout functions are implemented in the upper chip. This reduces pixel size by a factor of 2, thereby enhancing the spatial resolution of the detector. Due to the complexity of the SOI-3D process, a test system is required to verify the manufacture of 3-D integration as well as the design of separate chips. It is developed based on the IPbus protocol, which offers reliable operation and flexible test procedures. To disentangle the debugging of the test system and the investigation of chip defects, a field-programmable gate array (FPGA)-based emulator was designed to replace the CPV-4 real chip to verify the functionality of the test system itself. A joint test has validated the test system before it is used to evaluate the chip design and fabrication process of SOI-3D.