IEEE Transactions on Very Large Scale Integration (VLSI) Systems, volume 23, issue 8, pages 1429-1438
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation
Sho Endo
1
,
Yang Li
2
,
Naofumi Homma
1
,
Kazuo Sakiyama
2
,
Kazuo Ohta
2
,
Daisuke Fujimoto
3
,
Makoto Nagata
3
,
Toshihiro Katashita
4
,
Jean-Luc Danger
5
,
Takafumi Aoki
1
2
5
Laboratoire de Traitement et Communication de l’Information, Institut Telecom, Telecom ParisTech, Paris, France
|
Publication type: Journal Article
Publication date: 2015-08-01
Q1
Q2
SJR: 0.937
CiteScore: 6.4
Impact factor: 2.8
ISSN: 10638210, 15579999
Electrical and Electronic Engineering
Hardware and Architecture
Software
Abstract
In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and-or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.
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Endo S. et al. A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015. Vol. 23. No. 8. pp. 1429-1438.
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Endo S., Li Y., Homma N., Sakiyama K., Ohta K., Fujimoto D., Nagata M., Katashita T., Danger J., Aoki T. A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015. Vol. 23. No. 8. pp. 1429-1438.
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TY - JOUR
DO - 10.1109/tvlsi.2014.2339892
UR - https://doi.org/10.1109/tvlsi.2014.2339892
TI - A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation
T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AU - Endo, Sho
AU - Li, Yang
AU - Homma, Naofumi
AU - Sakiyama, Kazuo
AU - Ohta, Kazuo
AU - Fujimoto, Daisuke
AU - Nagata, Makoto
AU - Katashita, Toshihiro
AU - Danger, Jean-Luc
AU - Aoki, Takafumi
PY - 2015
DA - 2015/08/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 1429-1438
IS - 8
VL - 23
SN - 1063-8210
SN - 1557-9999
ER -
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BibTex (up to 50 authors)
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@article{2015_Endo,
author = {Sho Endo and Yang Li and Naofumi Homma and Kazuo Sakiyama and Kazuo Ohta and Daisuke Fujimoto and Makoto Nagata and Toshihiro Katashita and Jean-Luc Danger and Takafumi Aoki},
title = {A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
year = {2015},
volume = {23},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {aug},
url = {https://doi.org/10.1109/tvlsi.2014.2339892},
number = {8},
pages = {1429--1438},
doi = {10.1109/tvlsi.2014.2339892}
}
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Endo, Sho, et al. “A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, Aug. 2015, pp. 1429-1438. https://doi.org/10.1109/tvlsi.2014.2339892.