Institute of Electrical and Electronics Engineers (IEEE)

The Scaling of Cu-Cu Hybrid Bonding For High Density 3D Chip Stacking

Y KAGAWA ¹

S Hida ¹

Yuka Kobayashi ¹

K. Takahashi ¹

S Miyanomae ¹

M. Kawamura ¹

H. Kawashima ²

H Yamagishi ²

Takaya Hirano ²

K. Tatani ²

Hiroki Nakayama ¹

K. Ohno ²

H. Iwamoto ²

S. Kadomura ¹

Hide authors affiliations Show authors affiliations: 2 affiliations

Sony Semiconductor Manufacturing Corporation, Japan |

Sony Semiconductor Solutions Corporation, Japan |

Publication type: Proceedings Article

Publication date: 2019-03-01

Institute of Electrical and Electronics Engineers (IEEE)

DOI: 10.1109/EDTM.2019.8731186

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Abstract

We have successfully improved the scaling of Cu-Cu hybrid bonding. In this study, 3 um-pitch and 3M Cu-Cu connections with sufficient electrical properties and reliabilities were achieved. The ultra-fine pitch Cu-Cu connections correspond to the 0.75x scaling of conventional Cu-Cu hybrid bonding that we previously reported. Our high density 3D chip stacking technology is expected to enhance not only the function of back-illuminated CMOS image sensors (BI-CIS) but also that of coming 3D stacked semiconductor devices.

Found

1 citation

Popov Victor

PhD in Chemistry

36 publications, 202 citations

h-index: 8

Moscow Institute of Physics and Technology

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Institute of Electrical and Electronics Engineers (IEEE)