IEEE Journal of Solid-State Circuits, volume 48, issue 8, pages 1943-1953

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

Eustace Painkras 1
Luis A. Plana 1
Jim Garside 1
Steve Temple 1
Francesco Galluppi 1
Cameron Patterson 1
David R Lester 1
Andrew D Brown 2
Steve B Furber 1
Publication typeJournal Article
Publication date2013-08-01
Q1
Q1
SJR2.876
CiteScore11.0
Impact factor4.6
ISSN00189200, 1558173X
Electrical and Electronic Engineering
Abstract
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm 2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.

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Painkras E. et al. SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation // IEEE Journal of Solid-State Circuits. 2013. Vol. 48. No. 8. pp. 1943-1953.
GOST all authors (up to 50) Copy
Painkras E., Plana L. A., Garside J., Temple S., Galluppi F., Patterson C., Lester D. R., Brown A. D., Furber S. B. SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation // IEEE Journal of Solid-State Circuits. 2013. Vol. 48. No. 8. pp. 1943-1953.
RIS |
Cite this
RIS Copy
TY - JOUR
DO - 10.1109/jssc.2013.2259038
UR - https://doi.org/10.1109/jssc.2013.2259038
TI - SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation
T2 - IEEE Journal of Solid-State Circuits
AU - Painkras, Eustace
AU - Plana, Luis A.
AU - Garside, Jim
AU - Temple, Steve
AU - Galluppi, Francesco
AU - Patterson, Cameron
AU - Lester, David R
AU - Brown, Andrew D
AU - Furber, Steve B
PY - 2013
DA - 2013/08/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 1943-1953
IS - 8
VL - 48
SN - 0018-9200
SN - 1558-173X
ER -
BibTex |
Cite this
BibTex (up to 50 authors) Copy
@article{2013_Painkras,
author = {Eustace Painkras and Luis A. Plana and Jim Garside and Steve Temple and Francesco Galluppi and Cameron Patterson and David R Lester and Andrew D Brown and Steve B Furber},
title = {SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation},
journal = {IEEE Journal of Solid-State Circuits},
year = {2013},
volume = {48},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {aug},
url = {https://doi.org/10.1109/jssc.2013.2259038},
number = {8},
pages = {1943--1953},
doi = {10.1109/jssc.2013.2259038}
}
MLA
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MLA Copy
Painkras, Eustace, et al. “SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.” IEEE Journal of Solid-State Circuits, vol. 48, no. 8, Aug. 2013, pp. 1943-1953. https://doi.org/10.1109/jssc.2013.2259038.
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