volume 4 issue 2 pages 163-176

: Cost Based Hardware Optimization for Asymmetric Multicore Processors

Jyothi Krishna Viswakaran Sreelatha 1
Shankar Balachandran 2
Rupesh Nasre 1
Publication typeJournal Article
Publication date2018-04-01
Hardware and Architecture
Information Systems
Control and Systems Engineering
Abstract
Heterogeneous Multiprocessors (HMPs) are popular due to their energy efficiency over Symmetric Multicore Processors (SMPs). Asymmetric Multicore Processors (AMPs) are a special case of HMPs where different kinds of cores share the same instruction set, but offer different power-performance trade-offs. Due to the computational-power difference between these cores, finding an optimal hardware configuration for executing a given parallel program is quite challenging. An inherent difficulty in this problem stems from the fact that the original program is written for SMPs. This challenge is exacerbated by the interplay of several configuration parameters that are allowed to be changed in AMPs. In this work, we propose a probabilistic method named CHOAMP to choose the bestavailable hardware configuration for a given parallel program. Selection of a configuration is guided by a user-provided run-time property such as energy-delay-product (EDP) and CHOAMP aspires to optimize the property in choosing a configuration. The core part of our probabilistic method relies on identifying the behavior of various program constructs in different classes of CPU cores in the AMP, and how it influences the cost function of choice. We implement the proposed technique in a compiler which automatically transforms a code optimized for SMP to run efficiently over an AMP, eliding requirement of any user annotations. CHOAMP transforms the same source program for different hardware configurations based on different user requirement. We evaluate the efficiency of our method for three different run-time properties: execution time, energy consumption, and EDP, in NAS Parallel Benchmarks for OpenMP. Our experimental evaluation shows that CHOAMP achieves an average of 65, 28, and 57 percent improvement over baseline HMP scheduling while optimizing for energy, execution time, and EDP, respectively.
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Sreelatha J. K. V., Balachandran S., Nasre R. : Cost Based Hardware Optimization for Asymmetric Multicore Processors // IEEE Transactions on Multi-Scale Computing Systems. 2018. Vol. 4. No. 2. pp. 163-176.
GOST all authors (up to 50) Copy
Sreelatha J. K. V., Balachandran S., Nasre R. : Cost Based Hardware Optimization for Asymmetric Multicore Processors // IEEE Transactions on Multi-Scale Computing Systems. 2018. Vol. 4. No. 2. pp. 163-176.
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RIS Copy
TY - JOUR
DO - 10.1109/tmscs.2018.2791955
UR - https://doi.org/10.1109/tmscs.2018.2791955
TI - : Cost Based Hardware Optimization for Asymmetric Multicore Processors
T2 - IEEE Transactions on Multi-Scale Computing Systems
AU - Sreelatha, Jyothi Krishna Viswakaran
AU - Balachandran, Shankar
AU - Nasre, Rupesh
PY - 2018
DA - 2018/04/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 163-176
IS - 2
VL - 4
SN - 2332-7766
ER -
BibTex |
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BibTex (up to 50 authors) Copy
@article{2018_Sreelatha,
author = {Jyothi Krishna Viswakaran Sreelatha and Shankar Balachandran and Rupesh Nasre},
title = {: Cost Based Hardware Optimization for Asymmetric Multicore Processors},
journal = {IEEE Transactions on Multi-Scale Computing Systems},
year = {2018},
volume = {4},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {apr},
url = {https://doi.org/10.1109/tmscs.2018.2791955},
number = {2},
pages = {163--176},
doi = {10.1109/tmscs.2018.2791955}
}
MLA
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Sreelatha, Jyothi Krishna Viswakaran, et al. “: Cost Based Hardware Optimization for Asymmetric Multicore Processors.” IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 2, Apr. 2018, pp. 163-176. https://doi.org/10.1109/tmscs.2018.2791955.