Open Access
Open access
Science, volume 345, issue 6197, pages 668-673

A million spiking-neuron integrated circuit with a scalable communication network and interface

Paul A Merolla 1
John V Arthur 1
Rodrigo Alvarez Icaza 1
Andrew S. Cassidy 1
Jun Sawada 2
Filipp Akopyan 1
Bryan L. Jackson 1
Nabil Imam 3
Chen Guo 4
Yutaka Nakamura 5
Bernard Brezzo 6
Ivan Vo 2
Steven K. Esser 1
Rathinakumar Appuswamy 1
Brian Taba 1
Arnon Amir 1
Myron D Flickner 1
William P. Risk 1
Rajit Manohar 7
Dharmendra S. Modha 1
1
 
IBM Research–Almaden, 650 Harry Road, San Jose, CA 95120, USA.
2
 
IBM Research–Austin, 11501 Burnet Road, Austin, TX 78758, USA.
4
 
IBM Engineering and Technology Services, San Jose Design Center, 650 Harry Road, San Jose, CA 95120, USA.
5
 
IBM Research–Tokyo, Nippon Building Fund Toyosu Canal Front Building, 5-6-52 Toyosu, Koto-ku Tokyo 135-8511, Japan.
6
 
IBM T. J. Watson Research Center, 101 Kitchawan Road, Yorktown Heights, NY 10598, USA.
Publication typeJournal Article
Publication date2014-08-08
Journal: Science
Q1
Q1
SJR11.902
CiteScore61.1
Impact factor44.7
ISSN00368075, 10959203
Multidisciplinary
Abstract
Modeling computer chips on real brains Computers are nowhere near as versatile as our own brains. Merolla et al. applied our present knowledge of the structure and function of the brain to design a new computer chip that uses the same wiring rules and architecture. The flexible, scalable chip operated efficiently in real time, while using very little power. Science, this issue p. 668 A large-scale computer chip mimics many features of a real brain. Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.

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Cite this
GOST |
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GOST Copy
Merolla P. A. et al. A million spiking-neuron integrated circuit with a scalable communication network and interface // Science. 2014. Vol. 345. No. 6197. pp. 668-673.
GOST all authors (up to 50) Copy
Merolla P. A., Arthur J. V., Alvarez Icaza R., Cassidy A. S., Sawada J., Akopyan F., Jackson B. L., Imam N., Guo C., Nakamura Y., Brezzo B., Vo I., Esser S. K., Appuswamy R., Taba B., Amir A., Flickner M. D., Risk W. P., Manohar R., Modha D. S. A million spiking-neuron integrated circuit with a scalable communication network and interface // Science. 2014. Vol. 345. No. 6197. pp. 668-673.
RIS |
Cite this
RIS Copy
TY - JOUR
DO - 10.1126/science.1254642
UR - https://doi.org/10.1126/science.1254642
TI - A million spiking-neuron integrated circuit with a scalable communication network and interface
T2 - Science
AU - Merolla, Paul A
AU - Arthur, John V
AU - Alvarez Icaza, Rodrigo
AU - Cassidy, Andrew S.
AU - Sawada, Jun
AU - Akopyan, Filipp
AU - Jackson, Bryan L.
AU - Imam, Nabil
AU - Guo, Chen
AU - Nakamura, Yutaka
AU - Brezzo, Bernard
AU - Vo, Ivan
AU - Esser, Steven K.
AU - Appuswamy, Rathinakumar
AU - Taba, Brian
AU - Amir, Arnon
AU - Flickner, Myron D
AU - Risk, William P.
AU - Manohar, Rajit
AU - Modha, Dharmendra S.
PY - 2014
DA - 2014/08/08
PB - American Association for the Advancement of Science (AAAS)
SP - 668-673
IS - 6197
VL - 345
SN - 0036-8075
SN - 1095-9203
ER -
BibTex |
Cite this
BibTex (up to 50 authors) Copy
@article{2014_Merolla,
author = {Paul A Merolla and John V Arthur and Rodrigo Alvarez Icaza and Andrew S. Cassidy and Jun Sawada and Filipp Akopyan and Bryan L. Jackson and Nabil Imam and Chen Guo and Yutaka Nakamura and Bernard Brezzo and Ivan Vo and Steven K. Esser and Rathinakumar Appuswamy and Brian Taba and Arnon Amir and Myron D Flickner and William P. Risk and Rajit Manohar and Dharmendra S. Modha},
title = {A million spiking-neuron integrated circuit with a scalable communication network and interface},
journal = {Science},
year = {2014},
volume = {345},
publisher = {American Association for the Advancement of Science (AAAS)},
month = {aug},
url = {https://doi.org/10.1126/science.1254642},
number = {6197},
pages = {668--673},
doi = {10.1126/science.1254642}
}
MLA
Cite this
MLA Copy
Merolla, Paul A., et al. “A million spiking-neuron integrated circuit with a scalable communication network and interface.” Science, vol. 345, no. 6197, Aug. 2014, pp. 668-673. https://doi.org/10.1126/science.1254642.
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