Manufacturing technology of intra- and interchip interconnects for modern ULSIs: Review and concepts of development

Technological operations involved in manufacturing multilevel ULSI interconnections by the dual damascene (DD) method have been analyzed. Problem issues are considered, including (i) etching of porous intralevel insulation with ultralow values of dielectric constant, (ii) application of metal barrier and seed layers onto the porous surface of etched dielectric spacers, in which copper conductors have to be formed, (iii) low mechanical strength of porous dielectric spacers between copper conductors, (iv) insufficient stability of copper conductors with respect to failures as a result of electromigration, and (v) rapid growth in the resistivity of copper conductors with decreasing width, and limited possibility of compensating this factor by increasing conductor height (thickness). Possible approaches to solving these problems are proposed. According to one of these, horizontal copper conductors are formed first and then a porous dielectric is incorporated into the gaps between conductors by the method of chemical sol-gel deposition from solution by spin-on-dielectric (SOD) method on a centrifuge. The horizontal conductors can then be formed by the standard single-damascene process of copper deposition into temporal mask that is subsequently removed and replaced by the porous dielectric. According to another method, copper conductors are formed by local electrochemical deposition on the wafer surface that is preliminary covered by the barrier layer (BL), seed layer (SL), and a temporal mask, in which a pattern of conductors is prepared by etching down to the SL surface. In this case, the deposited copper conductors initially possess a textured crystalline structure, which facilitates the formation of elongated crystallites during subsequent thermal recrystallization. The surface of conductors can be also covered by local electrochemical process with an electroless barrier layer (e.g., of CoWP). Then, the BL and SL are removed and a porous ultralow-dielectric-constant insulator is incorporated into the gaps between copper conductors. The next stage of forming interconnections in multicrystal ULSIs consists of a three-dimensional (3D) vertical assembly of thinned chips by connecting them with copper conductors formed using through substrate via (TSV) technology. In order to improve heat removal from the assembly and increase its mechanical strength, the filling of vertical through channels in chips by copper is supplemented by copper plating of side edges and the formation of microbumps on crystal surfaces.