Open Access
Open access
Journal of Digital Food Energy & Water Systems, volume 5, issue 1

Deep Learning Algorithm Analysis of Potato Disease Classification for System on Chip Implementation

John Adebisi
Sesham Srinu
Varqa Mitonga
Publication typeJournal Article
Publication date2024-06-30
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ISSN27094510, 27094529
Abstract

Recently, every aspect of human existence has been affected by modern technologies including agriculture. The broad range of crops has witnessed setbacks in different capacities due to climate change among other factors, hence leading to diseases and infections; thereby leading to negatively impacted nutrition. This work uses a deep learning algorithm to investigate the classification of potato diseases as a case study which can be leveraged on by other agricultural products for reference.  Potatoes play a vital role in global agriculture, constituting a significant portion of fresh produce consumption. In southern Africa, potatoes hold particular importance, comprising 39% of total fresh produce consumption. However, the industry faces challenges from diseases such as early blight and late blight, resulting in substantial yield losses. Early detection is crucial, prompting the exploration of Convolutional Neural Networks (CNNs) for their disease classification capabilities. CNNs have shown excellent results in plant disease classification based on image data set. This study proposes the potential of aligning existing software-based Central Processing Units (CPUs) and Graphic Processing Units (GPUs) with FPGA-based potato disease classification using CNNs. To this end, five CNN models were trained on the Plant Village dataset for analysis. The models were compared using various performance metrics such as sensitivity, F1-Score, precision and recall. Based on the analysis the most suitable CNN model for FPGA implementation was selected. The chosen model was optimized for size using quantization technique. Subsequently the model was converted to Hardware Description Language (HDL) using Vitis High level synthesis (HLS) tool performance in terms of resources required to implement the model in System on Chip (SoC) was analysed.

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