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Proceedings of the National Academy of Sciences of the United States of America, volume 106, issue 48, pages 20155-20158

Four-dimensional address topology for circuits with stacked multilayer crossbar arrays

Dmitri B. Strukov 1
R. Stanley Williams 1
1
 
Hewlett-Packard Laboratories, 1501 Page Mill Road, MS1123, Palo Alto, CA 94304
Publication typeJournal Article
Publication date2009-12-11
scimago Q1
SJR3.737
CiteScore19.0
Impact factor9.4
ISSN00278424, 10916490
Multidisciplinary
Abstract

We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.

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