Advanced Fabrication Processes for Superconductor Electronics: Current Status and New Developments

In superconductor electronics fabrication processes developed at MIT Lincoln Laboratory, Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten superconducting layers. We discuss the effects of this placement and other processing factors on uniformity of JJ critical current across 200-mm wafers; specifically, nonuniformity of residual stress in Nb films, wafer bow and warpage caused by accumulated stress in the underlying dielectric and superconducting layers, and effects of accumulated topography caused by patterning and planarization of wiring layers. We describe the typical fabrication defects, focusing primarily on the peculiar defects caused by electrochemical corrosion of dissimilar metals. To increase the integration scale and enhance fabrication capabilities, we are developing a new process, titled SC1, in which Nb/Al/AlO _x /Nb JJs are placed near the bottom of the layer stack, preceded only by two planarized layers: resistor layer and superconducting ground plane. Six planarized Nb wiring layers are placed above the JJs. This layer stack should simplify routing of data and clock in integrated circuits, and allow for improvements in uniformity of small JJs. The SC1 process has a 250-nm minimum feature size for inductors, three sheet resistance options for resistors, and two options for JJ critical current density: 100 and 200 μA/μm ² . We present fabrication details and process optimization aimed at improving JJ uniformity, increasing circuit yield, and reducing occurrence of corrosion defects to below the 1 ppm level.