A very low-power quadrature VCO with back-gate coupling

Zolfaghari A., Razavi B.

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-μm digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.

Andreani P., Bonfanti A., Romano L., Samori C.

Vancorenland P., Steyaert M.S.

Tiebout M.

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

Behbahani F., Kishigami Y., Leete J., Abidi A.A.

This paper presents an in-depth treatment of mixers and polyphase filters, and how they are used in rejecting the image in transmitters and receivers. A powerful phasor-based analysis is used to explain all common image-reject topologies and their limitations, and it is shown how this can replace complex trigonometric equations commonly found in the literature. Practical problems in design and layout that limit the performance of image-reject upconversion and downconversion mixers are identified, and solutions are presented or limits explained. This understanding is put to work in a low-IF CMOS wideband, low-IF downconversion circuit, which repeatedly rejects the image by 60 dB over the wide band of 3.5 to 20 MHz without trimming or calibration.

Andreani P., Mattisson S.

This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 /spl mu/m CMOS process.

Hajimiri A., Lee T.H.

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors.

Matsuoka H., Tsukahara T.

The direct-conversion quadrature modulator described here was developed by using a frequency-doubling circuit technique so that the modulator and the local oscillator can be integrated on a single silicon chip. The local oscillation frequency in the modulator can be reduced to half the carrier frequency, and this enables the integration on a single chip. A three-level mixer with a newly designed symmetrical topology for two local oscillator inputs is used for the frequency doubling, so the image component levels of the modulated signals are low. When the modulator was implemented on a single chip by using Si-bipolar process technology with a cutoff frequency of 40 GHz, the image ratio at a carrier frequency of 5 GHz was less than -34 dBc.

Rofougaran A., Chang G., Rael J.J., Chang J.Y., Rofougaran M., Chang P.J., Djafari M., Ku M.-., Roth E.W., Abidi A.A., Samueli H.

A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the 900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS. It combines a digital frequency synthesizer, a double quadrature upconverter, an integrated oscillator, and a power amplifier with variable output. Data modulates a carrier hopping at 20 kHz with quaternary frequency-shift keying (4-FSK). At an output power level of +3 dBm, the harmonics and spurious tones lie at -52 dBc or below. When active, the transmitter drains 100 mA from 3 V.

Hyunchol Shin, Zhiwei Xu, Chang M.F.

Jalili M., Abbasalizadeh S.

Pant Y.R., Srinivasaraghavan S., Kuo Y., Gu B.

Chen X., Hu Y., Siriburanon T., Du J., Staszewski R.B., Zhu A.

Kumar M.

A low-power VCO circuit design with varying NMOS load and 3-transistors NAND gate and is presented. VCO circuit is designed with 180 nm gate length. Tuning of the output frequency is controlled by deviation in voltage (VCT) from 1.8 to 2.7 V. Additionally, a change in output frequency is achieved with the change in reverse bias (VSB) and drain-source biasing (VTune) of NMOS load. Three-stages VCO with power supply and drain-source voltage tuning of NMOS varactor provides frequency from 1.308 to 1.891 GHz with circuit power varying from 0.390 to 1.573 mW. By utilizing the substrate tuning of NMOS varactor load, the circuit gives frequency varying from 1.308 to 1.808 GHz. Frequency changes from 1.308 to 1.564 GHz have been obtained by changing the reverse bias of NMOS load with different source/drain biasing. The tuning range of 36, 32, and 18% has been obtained. VCO provides a phase noise of −94.33 dBc/Hz @1 MHz and figure of merit (FoM) for the VCO is 160.74 dBc/Hz. The reported VCO circuit provides an improved output frequency range with reduced power consumption.

Islam M.A., Ariful M., Jasir A.S., Pratyay A.A.

Bozorgi F., Sen P.

This work introduces a quadrature-voltage-controlled oscillator (QVCO) that employs the proposed hybrid back-gate and tail inductive coupling technique. The implemented QVCO on silicon occupies a die area of 0.03 mm2 in 22-nm FD-SOI technology. The power consumption of the QVCO operating with a 1-V supply voltage is 10.5 mW which, to the best of our knowledge, is comparable to the state of the art. The time and frequency-domain measurement results in the free-running mode show a phase noise (PN) of −112.1 dBc/Hz at 10-MHz offset from 60.2 GHz. The phase error throughout the whole tuning range is below 4.8°. At 10-MHz offset, the QVCO in this work achieves $FoM$ and ${FoM_{A}}$ of −177.5 and −192.7 dBc/Hz, respectively. They are in line among the bulk CMOS mm-wave QVCOs, despite the challenges imposed by short channel effects in 22-nm FD-SOI technology.

Oh N.

This paper proposes a subharmonic single-balanced RF receiver front-end (called LMV) where low noise amplifier is stacked on top of a differential voltage-controlled oscillator (VCO) to re-use the dc bias current. In this subharmonic (SH) LMV, the VCO itself plays the role of the single-balanced subharmonic mixer while generating an LO signal. This bottom LO SH LMV has good LO to IF and LO to RF leakage performances. Also, it can reduce the die size on a chip since it requires only one inductor for the VCO instead of two in the case of top LO LMV. Oscillating at around 2.4 GHz band, the proposed SH LMV is designed using a 65 nm CMOS technology and compared to the top LO SH LMV in terms of phase noise, conversion gain and double sideband noise figure. The SH LMVs consume about 160 μW dc power from a 1-V supply.

Jafari B., Tavakoli J., Sheikhaei S.

In this paper, a novel method of Super–Harmonic coupling is proposed to generate quadrature outputs. In this method, by direct connection of all switching transistors bulk terminals, a second harmonic current is injected from each one of the I/Q oscillators to the other. Therefore, the proposed circuit is called Body–Injected Super–Harmonic coupling (BISH–) QVCO. The quadrature operation of the proposed circuit is mathematically proven and certified by simulations. In addition, through a detailed analysis, closed–form expressions are derived for the output phase noise and phase error. To have a fair performance evaluation of the proposed topology, the proposed BISH-QVCO, and the conventional P–QVCO are designed and simulated in 0.18 ​μm RF-CMOS technology with 3.22–3.64 ​GHz oscillation frequency (12.25% tuning range), a power supply of 1.8V, and the same power consumption of 3.85 ​mW. The quality factor of the tank circuits is calculated as 9.2. Post layout simulation results predict phase noise of −122.3dBc/Hz at 1 ​MHz offset from 3.64 ​GHz oscillation frequency that presents 4.1 ​dB and 2.7 ​dB phase noise improvements compared to the conventional P–QVCO and simple LC VCO, respectively. The maximum I and Q outputs phase error due to a 2% tank capacitor mismatch is 7°. A FOM T of 189.4 ​dB is achieved for the proposed QVCO. Also, the proposed method is capable of generating multi – phase outputs, which can be ranked among the well-performing ones.

Jangra V., Kumar M.

In this paper, low power differential voltage-controlled oscillators (VCOs) have been reported utilizing the active load and inversion mode MOSFET (IMOS) varactor in the delay stages. VCO circuits operation is based on two NOR gates in differential mode, variations in gate control voltage of the NMOS/PMOS active load, and the varactor control voltage of IMOS. For VCO based on NMOS active load, variations in gate control voltage from 1.0 V to 2.0 V exhibit frequency variations from 6.687 GHz to 6.395 GHz. For VCO based on PMOS active load, variations in gate control voltage of PMOS active load from −0.5 V to 0.5 V provide frequency variations from 5.726 GHz to 6.142 GHz. For VCO based on IMOS varactor, variations in varactor control voltage of IMOS from 1.0 V to 2.0 V shows variations in output frequency from 3.796 GHz to 4.499 GHz with power dissipation of 2.06 mW. Proposed VCOs shows a phase noise of −76.20 dBc/Hz@1MHz for NMOS active load, −73.42 dBc/Hz@1MHz for PMOS active load and −75.63 dBc/Hz@1MHz for IMOS varactor load and the figure of merit (FoM) for the VCOs are −149.43 dBc/Hz, −145.58 dBc/Hz and −145.17 dBc/Hz, respectively.

Jangra V., Kumar M.

This paper proposes low power differential voltage-controlled oscillators (VCOs) with active load and IMOS varactor in delay stages. VCO circuits utilize two NOR gates in differential mode. The different levels of gate bias voltage ( V b i a s ) of the PMOS/NMOS active load along with variations in the varactor control voltage ( V c o n t r o l ) of inversion mode MOSFET (IMOS) achieves a wide frequency tuning range. PMOS active load VCO shows the output frequency range from 4.656 ​GHz to 5.333 ​GHz and power dissipation of 2.539 ​mW. NMOS active load VCO shows the output frequency range from 4.782 ​GHz to 5.516 ​GHz and power dissipation of 2.225 ​mW. The results with different width of varactor diode and bias voltages of active load are also reported in this work. Proposed VCO circuits are showing a phase noise of −102.37 dBc/Hz for PMOS active load, and −98.63 dBc/Hz for NMOS active load at 1 ​MHz offset with the corresponding figure of merit (FoM) of −172.86 dBc and −168.41 dBc, respectively.

Kochemasov D.V., Kuleshov V.N., Koptev G.I.

The paper contains short review of investigations connected with developments of quadrature voltage controlled oscillators and applications of such oscillators in modern communication systems. Three basic structures of the quadrature voltage controlled oscillators are considered and examples of their schematics are presented. Some papers containing theoretical analysis of such oscillators are discussed.

Kumar M.

In this work, voltage-controlled ring oscillator (VCO) by employing the three transistors (3T) XOR gates and NMOS varactor load has been reported. Output load has been varied with the application of reverse body bias voltage of NMOS transistor. VCO circuits with 3 and 5 delay stages have been designed. The output frequency is controlled by coarse and fine tuning techniques. The coarse tuning is provided with the variation in supply voltage (VCT) in the range of 1.8 V to 3.3 V. Further, fine tuning has been obtained with variation in reverse substrate bias voltage of NMOS varactor load from 0 to − 1 V. A three-stage VCO design shows output frequency deviation from 340.136 to 628.930 MHz and power consumption ranges from 0.1658 to 1.1285 mW with coarse tuning technique. Frequency deviation from 340.136 to 333.344 MHz and power consumption deviation from 0.1658 to 0.1648 mW have been obtained with fine tuning in three-stage VCO with fixed VCT of 1.8 V. A five-stage VCO design provides the output frequency from 189.035 to 328.947 MHz with power consumption range varying from 0.1698 mW to 1.1364 mW in coarse tuning mode. Moreover, five-stage VCO with fine tuning shows frequency variations from 328.947 to 326.797 MHz with varied power from 1.1364 to 1.1350 mW having the fixed VCT of 3.3 V. Results have been achieved with SPICE in 0.35-µm CMOS technology. An assessment of proposed VCO with previously reported circuits shows improvements in terms of output frequency range and power consumption.

Lin S., Chiou H.

This letter presents a complementary-injection-coupled technique to modify the conventional self-injection-coupled quadrature voltage-controlled oscillator (QVCO) topology. The proposed topology reduces the influence of dc offset problem at the source node of the coupling transistors that possibly makes the QVCO to fail and stop generating quadrature signals. Meanwhile, the modified coupling network provides an extra phase shift to resolve the bimodal oscillation. The QVCO is implemented in TSMC 0.18-μm CMOS technology. The measured phase noise is -111 dBc/Hz at 1-MHz offset, and the phase errors are from 0.29° to 1.39°. The figures of merit (FoM, FoM Q ) are -178.2 and -228.4 dBc/Hz, respectively. The chip area is 1.12 × 0.73 mm 2 .

Jafari B., Sheikhaei S.

In this paper, using an additional oscillator that operates at twice the main output frequency, super–harmonic coupling is created between two LC cross–coupled oscillators. The additional oscillator output signals are injected into the two main oscillators in a special way, such that in addition to forcing those oscillators to work in quadrature mode, a tail current shaping technique is performed on them, through the same circuit path. As a result, the main oscillators output phase noise is reduced. The second harmonic signals with the help of two additional NMOS transistors shape the gate voltages and consequently the drain current of the tail transistors. The quadrature mode operation of the proposed circuit is mathematically proved and the intrinsic tail current shaping behavior of it is analyzed. The proposed QVCO is designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V and a total power consumption of 4.4 mW at 2 GHz center frequency with 5.5% tuning rage. Simulation results confirm the proposed quadrature mode operation. It also shows the phase noise of −128.1 dBc/Hz for the proposed QVCO at 1 MHz offset and 1.92 GHz carrier, which is 9.3 dB better than that of the conventional Parallel (P)–QVCO. The maximum phase error for 0.5% I and Q tank capacitor mismatch is 1.47°.

Jiang R., Noori H., Dai F.F.

This paper presents a novel coupled oscillator RFIC for multi-phase clock generation. The design achieves low phase noise while maintaining strong coupling among oscillator cores. The proposed transformer-based dual-tank topology forms a loop of coupling path for enhanced multi-phase coupling. To facilitate strong magnetic coupling among oscillator cores, the proposed transformers utilize resonant inductive coupling to enhance the voltage swing at the coupled wing. The phase noise optimization is accomplished by leveraging the adaptive biasing feedback and the enhanced dual-tank technique. The behavioral model based on Alder's equation as well as the analysis of the tank response is given. Full electromagnetic (EM) modeling involving all transformers and the passive interconnecting routes has been performed using the EMX software in order to ensure that simulated performance reflects measurement environment. The prototype RFIC of the proposed circuit with eight phases is implemented in a 65-nm CMOS radio frequency (RF) silicon on insulator technology. The measured phase noise is -124.3 dBc/Hz at 1-MHz offset from 2.41 GHz with 7-mW power consumption per core, and the operating frequency can be digitally tuned from 1.81 to 2.41 GHz. The phase noise can be further improved to -128.2 dBc/Hz at 1-MHz offset from 2.41 GHz by increasing the power consumption to 15 mW per core.