IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 34, issue 10, pages 1537-1557

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Filipp Akopyan 1
Jun Sawada 1
Andrew Cassidy 1
Rodrigo Alvarez Icaza 1
John Arthur 1
Paul Merolla 1
Nabil Imam 1
Yutaka Nakamura 2
Pallab Datta 1
Gi-Joon Nam 3
Brian Taba 1
Michael Beakes 4
Bernard Brezzo 4
Jente B Kuang 3
Rajit Manohar 5
William P. Risk 1
Bryan Jackson 1
Dharmendra S. Modha 1
1
 
IBM Research—Almaden, San Jose, CA, USA
2
 
IBM Research–Tokyo, Tokyo, Japan
3
 
IBM Research—Austin, Austin, TX, USA
4
 
IBM’s T. J. Watson Research Center, Yorktown Heights, NY, USA
Publication typeJournal Article
Publication date2015-10-01
Q1
Q2
SJR0.957
CiteScore5.6
Impact factor2.7
ISSN02780070, 19374151
Electrical and Electronic Engineering
Computer Graphics and Computer-Aided Design
Software
Abstract
The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation, low-power consumption and scalability, which require a radical departure from conventional system design. Brain-inspired architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software. With such aggressive design metrics and the TrueNorth architecture breaking path with prevailing architectures, it is clear that conventional computer-aided design (CAD) tools could not be used for the design. As a result, we developed a novel design methodology that includes mixed asynchronous-synchronous circuits and a complete tool flow for building an event-driven, low-power neurosynaptic chip. The TrueNorth chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. To reduce the system's communication energy, we have adapted existing application-agnostic very large-scale integration CAD placement tools for mapping logical neural networks to the physical neurosynaptic core locations on the TrueNorth chips. With that, we have successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower power consumption than the same algorithms run on von Neumann architectures. The TrueNorth chip and its tool flow serve as building blocks for future cognitive systems, and give designers an opportunity to develop novel brain-inspired architectures and systems based on the knowledge obtained from this paper.

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Akopyan F. et al. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. Vol. 34. No. 10. pp. 1537-1557.
GOST all authors (up to 50) Copy
Akopyan F., Sawada J., Cassidy A., Alvarez Icaza R., Arthur J., Merolla P., Imam N., Nakamura Y., Datta P., Nam G., Taba B., Beakes M., Brezzo B., Kuang J. B., Manohar R., Risk W. P., Jackson B., Modha D. S. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. Vol. 34. No. 10. pp. 1537-1557.
RIS |
Cite this
RIS Copy
TY - JOUR
DO - 10.1109/TCAD.2015.2474396
UR - https://doi.org/10.1109/TCAD.2015.2474396
TI - TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
T2 - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AU - Akopyan, Filipp
AU - Sawada, Jun
AU - Cassidy, Andrew
AU - Alvarez Icaza, Rodrigo
AU - Arthur, John
AU - Merolla, Paul
AU - Imam, Nabil
AU - Nakamura, Yutaka
AU - Datta, Pallab
AU - Nam, Gi-Joon
AU - Taba, Brian
AU - Beakes, Michael
AU - Brezzo, Bernard
AU - Kuang, Jente B
AU - Manohar, Rajit
AU - Risk, William P.
AU - Jackson, Bryan
AU - Modha, Dharmendra S.
PY - 2015
DA - 2015/10/01
PB - Institute of Electrical and Electronics Engineers (IEEE)
SP - 1537-1557
IS - 10
VL - 34
SN - 0278-0070
SN - 1937-4151
ER -
BibTex |
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BibTex (up to 50 authors) Copy
@article{2015_Akopyan,
author = {Filipp Akopyan and Jun Sawada and Andrew Cassidy and Rodrigo Alvarez Icaza and John Arthur and Paul Merolla and Nabil Imam and Yutaka Nakamura and Pallab Datta and Gi-Joon Nam and Brian Taba and Michael Beakes and Bernard Brezzo and Jente B Kuang and Rajit Manohar and William P. Risk and Bryan Jackson and Dharmendra S. Modha},
title = {TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
year = {2015},
volume = {34},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
month = {oct},
url = {https://doi.org/10.1109/TCAD.2015.2474396},
number = {10},
pages = {1537--1557},
doi = {10.1109/TCAD.2015.2474396}
}
MLA
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MLA Copy
Akopyan, Filipp, et al. “TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, Oct. 2015, pp. 1537-1557. https://doi.org/10.1109/TCAD.2015.2474396.
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