Deep cryogenic silicon etching for 3D integrated capacitors: A numerical perspective

One promising approach to increase the capacity density of integral microcapacitors, microsupercapacitors, and microbatteries is three-dimensional structure design, where electrodes are exposed in three dimensions instead of conventional in-plane electrodes. Such structures include nanowires, nanotubes, nanopillars, nanoholes, nanosheets, and nanowalls. In this work, a cryogenic silicon etching process suitable for fabrication of structures with high electrode area is proposed. A numeric model of this process is experimentally calibrated and used for pillar array structure sidewall area optimization. The use of adaptive Runge–Kutta–Fehlberg time integrator allows to achieve almost linear overall computation complexity as a function of simulated etching time, despite the linear increase in conductance computation complexity with depth. A rule for choosing optimal geometric structure parameters under technological constraints is formulated. An optimized trefoil-like structure is proposed, resulting in a total 5.5% increase in sidewall area with respect to the hexagonal array of circular pillars, resulting in 20.33 sidewall area per unit chip area for 30 min long etch or 31.80 for 60 min long etch.