Impact of plasma induced damage on the fabrication of 3D NAND flash memory

• Plasma induced etching damage damages the crystallinity in Silicon substrate. • The damage is stored during the etching simulation as a surface property. • A low-energy post-etch treatment removes the damaged layer. • Selective epitaxial growth depends on crystalline quality of Silicon substrate. A physical process model for dry plasma etching is presented and applied to simulate vertical channel hole etching, a critical fabrication step in modern three-dimensional (3D) NAND flash memory. The presence of physical etching with high energy ions is shown to induce damage in the underlying silicon, which results in the formation of voids during the subsequent selective epitaxial growth (SEG) step. In this manuscript, we present a model for ion induced damage by storing it as a surface property during the plasma etching simulation. A specialized advection algorithm is subsequently applied to simulate silicon SEG on the bottom source line. The model clearly shows the damage caused by the high energy particles, on the crystal nature of silicon, resulting in poor coverage during the SEG step. The removal of this damaged layer using lower energy plasmas results in highly crystalline epitaxially grown silicon. The simulation results show excellent agreement with experiments in the formation of undesired voids without the low-energy pre-epitaxial plasma treatment.