Korea Advanced Institute of Science and Technology

Kim D., Chae J., Park K., Moon G.

Chae D., Jung W., Kim K., Seok W., Shim M.

Park G., Kim H.

Woo S., Shin Y., Rhee J., Lee H., Kim H., Ahn S.

Choi K., Kim I., Lee S., Huh J.

The CXL (Compute Express Link) technology is an emerging memory interface with high-level commands. Recent studies applied the CXL memory expanding technique to mitigate the capacity limitation of the conventional DDRx memory. Unlike the prior studies to use the CXL memory as the capacity expander, this study proposes to use the CXL-based memory as a secure main memory device, while removing the conventional memory. In the conventional DDRx memory, to provide confidentiality, integrity, replay protection, and obliviousness, costly mechanisms such as counter-based integrity trees and location shuffling by ORAM (Oblivious RAM) are used. Such mechanisms incur significant performance degradation in the current DDR-based memory systems, and their costs increase as the capacity of the memory increases. To mitigate the performance degradation, the prior work proposed an obfuscated channel for a secure memory module enclosing its controller in the package. Based on the approach, we propose a secure CXL-only memory architecture called ShieldCXL . It uses the channel encryption and integrity protection mechanism of the CXL interface to provide a practical ORAM while supporting confidentiality, integrity, and replay protection from physical attacks and rowhammers. To protect the PCIe-connected memory expanding board, this study proposes to use the standard physical sealing technique to detect physical intrusion. To mitigate the increased latency with the sealed CXL memory module, the study further optimizes performance by adopting an in-package DRAM cache. In addition, this study investigates destination obfuscation when a CXL switch is used to route among multiple hosts and memory devices. The evaluation shows that ShieldCXL provides 9.16x performance improvements over the prior ORAM technique.

Hur I., Xia W., Kang K.

Koo K., Lee J.

Modern storage technologies aim to enhance performance and lower costs. With advances in storage devices, numerous studies propose key-value store designs for heterogeneous storage systems. Many rely on the Log-Structured Merge-Tree(LSM), which optimizes write-heavy workloads and flash storage. However, LSM-tree-based key-value stores on heterogeneous storage systems suffer from severe performance degradation and a surge in query latency. A key issue is write stall constraints , which arise from considering only single-tier storage, limiting key-value stores from leveraging multi-tier architectures. Another problem with key-value stores for heterogeneous storage systems is the inter-storage imbalance . Performance discrepancies between storage tiers fluctuate due to each storage device’s differing storage media technologies and garbage collection mechanisms. Consequently, existing hierarchical storage-based key-value stores (HSKVS) do not fully utilize the resources of storage devices across tiers and do not account for the performance imbalance between storage tiers. This paper presents an I/O scheduler designed to maintain data balance across storage tiers of multi-tiered storage engines. Our approach leverages two key techniques: dynamic data layout and flush I/O throttling . Dynamic data layout optimizes data placement by adapting to performance metrics and workload demands. This approach ensures data is stored in the most appropriate tier, improving access times and reducing latency. Meanwhile, flush I/O throttling aims to efficiently manage the I/O workload by controlling data movement between memory and storage. It balances data flow, preventing bottlenecks, especially during peak usage. To evaluate the effectiveness of our proposed I/O scheduler, we integrated it into a conventional HSKVS system. This integration achieved up to a 14.7 × performance improvement on YCSB workload D compared to conventional HSKVS systems. Furthermore, our proposed scheduler reduced the tail latency for get queries by about 9.3 × , from 13 ms to 1.4 ms.

Jeon S.S., Jeon H., Lee J., Haaring R., Lee W., Nam J., Cho S.J., Lee H.

Kimjeon J., Shim J.

Yoon J., Choi W., Lee W.H., Lee G.B., Choi B.W., Kim P., Heo Y., Kim D.G., Kim H.A., Bae M.A., Kim S.S., Lee E.Y., Oh C., Lee H.J., Kim H.W., et. al.

Baek K., Hwang E., Lee J.

Lee N., Lee J., Oh S., Lee R., Yeo H., Kim Y., Lee J.

Nam H.S., Kang D.O., Han J., Kim J.W., Yoo H.

Seo D., Cho G.Y., Slager R.

Lee J.W., Lee J., Kim J.Y., Bang J., Jeon S.S., Lee H., Lee S.Y.