Recent Advances in Reactive Ion Etching and Applications of High-Aspect-Ratio Microfabrication

Gerlt M.S., Läubli N.F., Manser M., Nelson B.J., Dual J.

Deep reactive ion etching (DRIE) with the Bosch process is one of the key procedures used to manufacture micron-sized structures for MEMS and microfluidic applications in silicon and, hence, of increasing importance for miniaturisation in biomedical research. While guaranteeing high aspect ratio structures and providing high design flexibility, the etching procedure suffers from reactive ion etching lag and often relies on complex oxide masks to enable deep etching. The reactive ion etching lag, leading to reduced etch depths for features exceeding an aspect ratio of 1:1, typically causes a height difference of above 10% for structures with aspect ratios ranging from 2.5:1 to 10:1, and, therefore, can significantly influence subsequent device functionality. In this work, we introduce an optimised two-step Bosch process that reduces the etch lag to below 1.5%. Furthermore, we demonstrate an improved three-step Bosch process, allowing the fabrication of structures with 6 μm width at depths up to 180 μm while maintaining their stability.

Frasca S., Leghziel R.C., Arabadzhiev I.N., Pasquier B., Tomassi G.F., Carrara S., Charbon E.

We present here, for the first time, a fabrication technique that allows manufacturing scallop free, non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. TSVs are among major technology players in modern high-volume manufacturing as they enable 3D chip integration. However, the usual standardized TSV fabrication process has to deal with scalloping, an imperfection in the sidewalls caused by the deep reactive ion etching. The presence of scalloping causes stress and field concentration in the dielectric barrier, thereby dramatically impacting the following TSV filling step, which is performed by means of electrochemical plating. So, we propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called “Michelangelo”, we obtained an extremely well polishing of the TSV holes, by reaching atomic-level smoothness and a record aspect ratio of 28:1. The Michelangelo step will thus drastically reduce the footprint of 3D structures and will allow unprecedented efficiency in 3D chip integration.

Zaman A., Alsolami A., Rivera I.F., Wang J.

This paper demonstrates how a single crystal silicon wafer can be used to fabricate thinfilm piezoelectric-on-silicon (TPoS) resonators by utilizing a modified version of Single Crystal Silicon Reactive Etch and Metallization (SCREAM) process. The developed process enables the fabrication of MEMS resonators with varied device layer thicknesses ranging from sub-micrometer to tens of micrometers (one thickness per die) from a single bulk silicon wafer, while avoiding the need of costly silicon-on-insulator (SOI) substrates. The thin-film piezoelectric on single-crystal silicon reactive etched technique allows batch fabrication of TPoS resonators, while also retaining the same number of photolithography steps. To maintain a good resonator body sidewall roughness, a conformal Al2O3 thin film was deposited by atomic layer deposition to act as the sidewall protection layer. Through the developed process, resonators with varied silicon layer ranging from 0.1μm to 47μm have been successfully implemented. The measured results under different ZnO-to-Si thickness ratios have been studied, in terms of motional impedance (Rm), quality factor (Q), and resonance frequency. It is noted that TPoS MEMS resonators operating in fundamental and higher lateral extensional modes exhibit their best performance under an optimal ZnO-to-Si thickness ratio. Resonators fabricated by the modified TPoS process with a Si device layer thickness of 4-20 μm exhibits optimal performance. The highest Q of 1,567 for a disk resonator and the lowest motional impedance of 791 Ω for a square plate resonator were achieved with Si layer thicknesses of 20 μm and 4 μm, respectively.

Yadavali S., Lee D., Issadore D.

We present a new, robust three dimensional microfabrication method for highly parallel microfluidics, to improve the throughput of on-chip material synthesis by allowing parallel and simultaneous operation of many replicate devices on a single chip. Recently, parallelized microfluidic chips fabricated in Silicon and glass have been developed to increase the throughput of microfluidic materials synthesis to an industrially relevant scale. These parallelized microfluidic chips require large arrays (>10,000) of Through Silicon Vias (TSVs) to deliver fluid from delivery channels to the parallelized devices. Ideally, these TSVs should have a small footprint to allow a high density of features to be packed into a single chip, have channels on both sides of the wafer, and at the same time minimize debris generation and wafer warping to enable permanent bonding of the device to glass. Because of these requirements and challenges, previous approaches cannot be easily applied to produce three dimensional microfluidic chips with a large array of TSVs. To address these issues, in this paper we report a fabrication strategy for the robust fabrication of three-dimensional Silicon microfluidic chips consisting of a dense array of TSVs, designed specifically for highly parallelized microfluidics. In particular, we have developed a two-layer TSV design that allows small diameter vias (d < 20 µm) without sacrificing the mechanical stability of the chip and a patterned SiO2 etch-stop layer to replace the use of carrier wafers in Deep Reactive Ion Etching (DRIE). Our microfabrication strategy allows >50,000 (d = 15 µm) TSVs to be fabricated on a single 4” wafer, using only conventional semiconductor fabrication equipment, with 100% yield (M = 16 chips) compared to 30% using previous approaches. We demonstrated the utility of these fabrication strategies by developing a chip that incorporates 20,160 flow focusing droplet generators onto a single 4” Silicon wafer, representing a 100% increase in the total number of droplet generators than previously reported. To demonstrate the utility of this chip for generating pharmaceutical microparticle formulations, we generated 5–9 µm polycaprolactone particles with a CV < 5% at a rate as high as 60 g/hr (>1 trillion particles/hour).

Laermer F., Urban A.

Luo X., Gianchandani Y.B.

This paper presents a microfabricated sensor that uses electrical microdischarges to sense the deflection of a diaphragm under applied pressure. The sensor responds by redistributing electron current of pulsed microdischarges between one cathode (K), a reference anode (A1), and a deflecting anode (A2), all of which are located in a cavity under the diaphragm; the differential anode current indicates the applied pressure. In this paper, the sensor is monolithically fabricated from a single silicon wafer, using a combination of surface micromachining and through-wafer isolated bulk-silicon lead transfer (TWIST) technology. The TWIST technology provides lead transfer into the sealed cavity as well as backside contacts, allowing miniaturization of the device footprint and surface mount assembly within systems. The active footprint of the complete sensor measures 300 × 300 μm 2 in size, making it the smallest sealed microdischarge-based pressure sensor reported to date. The normalized differential current from the anodes monotonically increases from -0.7 to 0.2 as the external pressure increases from 1 to 8 atm.

Li X., Chan K., Ramer R.

Pedersen M., Huff M.

This letter reports the research performed on the measurement of the repeatability of the resultant lateral dimensions across fused silica substrates that were etched using an inductively-coupled plasma reactive-ion etch process. We have developed and previously reported a highly-anisotropic plasma etch process with the demonstrated etch depths of over 100 microns deep into fused silica substrates and aspect ratios greater than 10 to 1. The across substrate repeatability of the lateral dimensions of the etched features is an extremely important parameter for any plasma etch process. The measured etched feature lateral dimensional repeatability for an average etch depth of 100 microns was found to be approximately 2.41% across each wafer over a total of 120 measurements taken. The capability to etch highly-anisotropic deep features with repeatable dimensional control into fused silica has important implications for a number of important MEMS applications.

Ozgur M., Pedersen M., Huff M.

Efimovskaya A., Lin Y., Shkel A.M.

This paper presents a miniature 50 mm 3 inertial measurement unit (IMU) implemented using a folded microelectromechanical systems (MEMS) process. The approach is based on wafer-level fabrication of high aspect-ratio single-axis sensors interconnected by flexible hinges and folded into a 3-D configuration, like a silicon Origami [1]. Two different materials for flexible hinges have been explored, including photo-definable polyimide and parylene-C. We report, for the first time, an IMU prototype with seven operational sensors: three accelerometers, three gyroscopes, and a prototype of a reference clock. This paper concludes with the results of experimental characterization of inertial sensors demonstrating the feasibility of the proposed approach for a compact IMU.

Pedersen M., Huff M.

Huff M., Pedersen M.

This paper reports a previously unreported anomaly that occurs when attempting to perform deep, highly anisotropic etches into fused silica using an Inductively-Coupled Plasma (ICP) etch process. Specifically, it was observed that the top portion of the etched features exhibited a substantially different angle compared to the vertical sidewalls that would be expected in a typical highly anisotropic etch process. This anomaly has been termed as “faceting.” A possible explanation of the mechanism that causes this effect and a method to eradicate it has been developed. Additionally, the method to eliminate the faceting is demonstrated. It is theorized that this faceting is a result of the interaction of the electro-potential electrical fields that surround the patterned nickel layers used as a hard mask and the electrical fields directing the high-energy ions from the plasma to the substrate surface. Based on this theory, an equation for calculating the minimum hard mask thickness required for a desired etch depth into fused silica to avoid faceting was derived. As validation, test samples were fabricated employing hard masks of thicknesses calculated based on the derived equation, and it was found that no faceting was observed on these samples, thereby demonstrating that the solution performed as predicted. Deep highly anisotropic etching of fused silica, as well as other forms of silicon dioxide, including crystalline quartz, using plasma etching, has an important application in the fabrication of several MEMS, NEMS, microelectronic, and photonic devices. Therefore, a method to eliminate faceting is an important development for the accurate control of the dimensions of deep and anisotropic etched features of these devices using ICP etch technology.

Ozgur M., Huff M.

This paper reports research performed on developing high rate of etch processes for the plasma etching of deep, highly anisotropic features into single-crystal 4H silicon carbide (SiC) substrates using an inductively coupled plasma process. To develop these etch processes, the authors conducted a design of experiments (DOE) whereby the most impactful etch process parameters were varied over predetermined values while the other etch process parameters were left unaffected. After performing an experimental etch on each sample, the samples were examined using various metrology methods to measure the etch outcomes. Using the investigational data accumulated during the DOE, the authors performed multiple regression analysis on this collected data in order to develop a model of the etch process that allows obtainment of desired outcomes, including a high etch rate, high mask selectivity, vertical sidewalls and minimal etch defects. Using optimized processes from the model, the authors were able to exhibit the ability to etch very deep features into SiC of more than 100 μm with nearly vertical sidewalls at high etch-rates. The capability to etch deep features at high etch rates into SiC is potentially useful for a number of microfabrication application areas.

Teo A.J., Li H., Tan S.H., Yoon Y.

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G−1, and a highest recorded sensitivity of 44.1 mV G−1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

Pedersen M., Huff M.

This paper reports research performed on developing and optimizing a process recipe for the plasma etching of deep high-aspect ratio features into fused silica (fused quartz) material using an inductively coupled plasma reactive-ion etch process. As part of this effort, we performed a design of experiments (DOE), wherein the etch recipe parameters having the most impact on the etch process were varied over fixed ranges of predetermined values, while the other etch recipe process parameters were unchanged. Subsequently, the etched samples were analyzed so as to quantify the etch outcomes. Using the experimental data collected during the DOE, we then performed multiple regression analysis on this data to determine optimal etch tool parameters in order to achieve the desired etch results. Based on this work, we have demonstrated the ability to etch very deep features into fused silica of over 100 microns, having nearly vertical sidewalls, and with aspect ratios of over 10 to 1 using the optimized etch process. The ability to fabricate deep high-aspect ratio features into fused silica has important implications for a number of micro-electromechanical systems applications. The etch technology developments presented herein are applicable to fused silica, as well as to other silicon-dioxide-based materials including crystalline quartz.

Ji H., Choi W., Choi E., Ji Y., Kim M., Jeon H., Kim D.W.

Wei J., Woo B., Lee D., Jeong K., Kwon K.

ABSTRACTIn this study, the etching characteristics of C4F6 gas are investigated using inductively coupled plasma (ICP) etching equipment to apply a high‐aspect‐ratio etching process to SiO2. The use of a CF4 + C4F6 + He gas mixture in the ICP etching system provides a lower F atom density, a higher polymerization capacity with increasing C4F6 gas proportion, and better SiO2/amorphous carbon layer selectivity. With an increase in the C4F6 gas mixing ratio, the bowing phenomenon is alleviated, and a vertically etched profile is formed regardless of the source and bias power. The etching characteristics demonstrate that ICP etching using C4F6 gas is an excellent alternative to capacitively coupled plasma (CCP) etching for the development of next‐generation high‐aspect‐ratio‐contact etching processes.

Zhou G., Shi F., Wang B., Tian Y., Zheng Z., Qiao S., Gong B., Guo S., Tie G.

Jia J., Guo B., Yang W., Qin J., Wu G., Li K., Zhu J., Zhang Z., Yao H.

Majumder T., Patowari P.K.

Atak A.Ç., Ünal E., Demir H.V.

Abstract Three-dimensional (3D) printing allows for the construction of complex structures. However, 3D-printing vertical structures with a high aspect ratio remains a pending challenge, especially when a high lateral resolution is required. Here, to address this challenge, we propose and demonstrate micro-3D sculptured metastructures with deep trenches of 1:4 (width:height) aspect ratio for sub-10 µm resolution. Our construction relies on two-photon polymerization for a 3D-pattern with its trenches, followed by electroplating of a thick metal film and its dry etching to remove the seed layer. To test the proposed fabrication process, we built up three-dimensional RF metastructures showcasing the depth effect as the third dimension. Using the numerical solutions, we custom-tailored these metastructure resonators to fall within a specific resonance frequency range of 4-6 GHz while undertaking comparative analyses regarding overall footprint, quality factor, and resonance frequency shift as a function of their cross-sectional aspect ratio. The proposed process flow is shown to miniaturize metal footprint and tune the resonance frequency of these thick 3D-metastructures while increasing their quality factor. These experimental findings indicate that this method of producing trenches via 3D-printing provides rich opportunities to implement high-aspect-ratio, complex structures.

Ahmed A.A., Alegret N., Almeida B., Alvarez-Puebla R., Andrews A.M., Ballerini L., Barrios-Capuchino J.J., Becker C., Blick R.H., Bonakdar S., Chakraborty I., Chen X., Cheon J., Chilla G., Coelho Conceicao A.L., et. al.

He S., Tian Y., Zhou H., Zhu M., Li C., Fang B., Hong Z., Jing X.

AbstractAs a popular artificial composite material emerging in recent years, metasurfaces are one of the most likely devices to break through the volume limitation of conventional optical components due to their compact structure, flexible materials, and high modulation resolution of the beam. With a unique arrangement of units or made of special materials, the metasurface can effectively modulate the incident light's amplitude, phase, polarization, and frequency, thus realizing applications such as communication, imaging, sensing, and beam steering. The interaction of high‐resolution structure, periodic arrangement, and unique constituent materials makes it possible to realize these applications, so researchers should choose the appropriate micro‐nano processing technologies when designing and preparing the metasurface. This review will present micro‐nano processing technologies related to the preparation of metasurfaces, such as electron beam lithography (EBL), femtosecond laser processing, focused ion beam lithography (FIB), additive manufacturing, nanoimprinting, and self‐assembly, respectively. In addition, classical lithography techniques such as wet lithography, plasma lithography, deep reactive ion etching (DRIE), and photolithography will be introduced. Their development history and functions are described in detail, and examples of these techniques in preparing micro‐nano‐structures in different branches are presented, as well as some examples of metasurface preparation using these techniques. In addition, this paper has produced several tables describing these technologies, outlining their resolution, processing materials, advantages and disadvantages, and so on. Hopefully, this review will provide researchers with options and ideas for preparing metasurfaces.

Zhang W., Dai S., Wu F., Pan S., Su J., Wu P., Cui L.

Nanostructures based on flexible material are essential for modulating reflected colors by actively changing the unit structure. However, current nanostructures face challenges in achieving active and efficient modulation across a broader spectral range. Here, we propose a stretchable color management method. The structure consists of a polydimethylsiloxane (PDMS) flexible substrate and cross-shaped lithium niobate (LiNbO3). This study achieves reflection color changes, continuous adjustment, and automatic switching of solar spectrum reflectance by optimizing the geometric structure. It shows that the spectral tuning range is larger, benefiting from the special nanostructures and the stretchability of PDMS, which result in a larger tunable period range and a maximum wavelength shift of nearly 180 nm. Moreover, this unique design has been effectively balanced and optimized to respond to different polarization waves. Finally, the sensing characteristics of the nanostructure are studied through its response to changes in the refractive index (RI). The results demonstrate a method with implications for flexible electronic devices, color generation, and biochemical sensing, contributing to progress in flexible wearable technology and green building.

Conlin S.K., Muhanga J.J., Parette D.N., Coridan R.H.

The use of metal oxide catalysts to enhance plasma CO2 reduction has seen significant recent development towards processes to reduce greenhouse gas emissions and produce renewable chemical feedstocks.

Shibanov D.R., Lopaev D.V., Maslakov K.I., Konnikova M.R., Rakhimov A.T.

Paula K.T., Clabel H. J.L., Vieira E.V., Mastelaro V.R., Vollet-Filho J.D., Mendonça C.R.

Kamiński M., Król K., Kwietniewski N., Myśliwiec M., Sochacki M., Stonio B., Kisiel R., Martychowiec A., Racka-Szmidt K., Werbowy A., Żelazko J., Niedzielski P., Szmidt J., Strójwąs A.

Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

Filipovic L., Reiter T.

Morozov O.V.