Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

Oprins H., Ramirez Bohorquez J.L., Vermeersch B., Van der Plas G., Beyne E.

Serbulova K., Chen S., Hellings G., Hiblot G., Veloso A., Jourdain A., De Boeck J., Groeseneken G., Horiguchi N.

Extremely thin wafers are an important enabler for high density nano Through Silicon Via (nTSV) in future system-technology co-optimization (STCO) scaling. Measurements and TCAD simulations indicate that reducing the wafer thickness to 0.3µm is beneficial to latch-up prevention because of lower β-gain, which is induced by the strong recombination in well-base regions.

Jourdain A., Schleicher F., De Vos J., Stucchi M., Chery E., Miller A., Beyer G., Van der Plas G., Walsby E., Roberts K., Ashraf H., Thomas D., Beyne E.

This paper presents a novel approach for extreme wafer thinning on carrier followed by nano-scale via-last formation in order to achieve sub-500nm pitch interconnects, electrically connecting the backside to the frontside of a device wafer. Indeed, it is expected that most of the 3D System-on-Chip (3D-SOC) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach, combined with via-last TSV (Through Silicon Vias) connections. To reach sub-500nm interconnect pitches, via-last TSV scaling is also expected to follow a similar trend. To do so, a dedicated sub-micron wafer thinning process was developed that enables a very tight thickness control over the entire wafer, with less than 70nm total thickness variation (TTV), and nano-TSV's were etched using a Bosch process applied to extremely small CD structures (180x250nm top CD). Functional electrical structures have been measured and characterized, showing up to 99% electrical yielding connections between frontside and backside of the device wafers.

Liang W., Gauthier R., Mitra S., Li Y., Yan C.

In this paper, Internal Latchup (ILU) behaviors are studied in an advanced bulk FinFET technology. The methodology of the ILU development and characterization are introduced and the ILU characteristics of thin oxide (SG) and thick oxide (EG) victim devices are discussed comprehensively. Comparison between 7nm and 14nm Bulk FinFET technology has been made on ILU characteristics.

Hiblot G., Van Huylenbroeck S., Van der Plas G., De Wachter B., Chasin A.V., Kaczer B., Chiarella T., Mitard J., De Muynck S., Beyer G., Beyne E.

In this work, the impact of 1x5μm Via-last integration on an advanced bulk FinFET technology is investigated. We find that mechanical impact of TSV proximity is below detection limit, however plasma-induced damage (PID) is observed on small devices (high antenna aspect ratio). Finally, a back-side anneal raising the TSV thermal budget shows no increase of mechanical impact though it partially cures PID damage on small devices.

Dai C.-., Chen S.-., Linten D., Scholz M., Hellings G., Boschke R., Karp J., Hart M., Groeseneken G., Ker M.-., Mocuta A., Horiguchi N.

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

Beyne E.

This overview article sheds light into the diverse notions and terms associated with 3-D circuits. It categorizes and classifies the various technologies/techniques and helps the experienced researcher as well as a newcomer to find an orientation in the complex 3-D landscape.

Chasin A., Scholz M., Guo W., Franco J., Potoms G., Jourdain A., Linten D., Van der Plas G., Absil P., Beyne E.

The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.

Tremouilles D., Natarajan M.I., Scholz M., Azilah N., Bafleur M., Sawada M., Hasebe T., Groeseneken G.

Voldman S.H., Nicholas Perez C., Watson A.

This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of “parameterized cell” guard ring structures concept into a Cadence™ based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations.

Quincke J.

Zappe H.P., Gupta R.K., Terrill K.W., Chenming Hu

Troutman R.R.

n-well guard rings have long been used for isolating potential electron injectors to avoid latch-up of CMOS circuits. Such guard rings are shown to be orders of magnitude more efficient for CMOS fabricated in an epitaxial layer (epi-CMOS) than for bulk (non-epi) CMOS. The maximum escape probability in epi-CMOS measures 3.9E-06 while for bulk CMOS it is 1.8E-02.

Lu Y., Wu M., Hu V.P.